1993
1994
(1) N. Yoshikawa, H. Ishibashi and M. Sugahara, "Dynamic Characteristics of Inverter Circuits Using Single Electron Transistor", Extended Abstract of 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp.334-336.
1995
(1) N. Yoshikawa, Y. Jinguu, H. Ishibashi and M. Sugahara, "Complementary Digital Logic Using Resistively Coupled Single Electron Transistor", Extended Abstract of 1995 International Conference on Solid State Devices and Materials, Osaka, 1995, pp.204-206.
(2) N. Miura, N. Yoshikawa and M. Sugahara, "Electrical Field Effect in Microbridges Made of NbN Granular Thin Films", Extended Abstracts of 5th International Superconductive Electronics Conference, 1995, Nagoya, Japan, pp.213-215.
(3) N. Yoshikawa, H. Su, K. Fukushima and M. Sugahara, "Study of Electron Conduction Properties of NbN thin Flms Using NbN/MgO/NbN Double Junction", Extended Abstracts of 5th International Superconductive Electronics Conference, 1995, Nagoya, Japan, pp.450-452.
1996
(1) N. Yoshikawa, H. Kimijima, N. Miura and M. Sugahara, "Single-Electron-Tunneling Effect in Nanoscale Granular Microbridge", Abstracts of 1996 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures (QDS '96), Sapporo, Japan, November 1996.
1997
(1) Z. J. Deng, N. Yoshikawa, U. Ghoshal, S. R. Whiteley and T. Van Duzer, "20 Gb/s Self-Timed Vector Processing with Josephson Single Flux Quantum Technology", Technical Digest, 1997 International Solid-State Circuit Conference (ISSCC'97), San Francisco, Feb. 6-8, 1997, pp. 128-129.
(2) N. Yoshikawa, Z. J. Deng, S. R. Whiteley and T. Van Duzer, "Design and Testing of Data-Driven Self-Timed RSFQ Shift Register", Extended Abstract of International Superconductive Electronics Conference (ISEC'97), Berlin, Germany, June, 1997, pp. 382-384.
(3) N. Yoshikawa, Z. J. Deng, S. R. Whiteley and T. Van Duzer, "Design and Testing of Data-Driven Self-Timed RSFQ Demultiplexer", Extended Abstract of International Superconductive Electronics Conference (ISEC'97), Berlin, Germany, June, 1997, pp. 353-355.
(4) Z. J. Deng, H. Zhang, N. Yoshikawa, U. Ghoshal, E. Fang, A. Flores, L. Zheng, S. R. Whiteley and T. Van Duzer, "Memory-Processor Interface with Hybrid CMOS-RSFQ Technology", Extended Abstract of International Superconductive Electronics Conference (ISEC'97), Berlin, Germany, June, 1997, pp. 347-349.
(5) Z. J. Deng, N. Yoshikawa, S. R. Whiteley and T. Van Duzer, "Asynchronous Design Methodology for RSFQ Digital System", Extended Abstract of International Superconductive Electronics Conference (ISEC'97), Berlin, Germany, June, 1997, pp. 332-334.
1998
(1) Z.J. Deng, N. Yoshikawa, J.A. Tiemo, S.R. Whiteley, T. Van Duzer, "Asynchronous circuits and systems in superconducting RSFQ technology", Proceeding of Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 98), San Diego, California, March, 1998.
(2) N. Yoshikawa, C. Fukuzato and M. Sugahara, "Single Electron Transfer Logic Gate Family", Abstracts of 1998 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures (QDS '98), Sapporo, Japan, May, 1998.
(3) N. Yoshikawa, H. Tago and K. Yoneyama, "Design Approach to RSFQ Logic Circuits Based on the Binary Decision Diagram", Abstract of 1998 Applied Superconductivity Conference (ASC98), Palm Desert, California, September, 1998.
(4) N. Yoshikawa, Z. J. Deng, H. Tago, K. Yoneyama and T. Van Duzer, "Design of Data-Driven Self-Timed RSFQ Vector Adder", Abstract of 1998 Applied Superconductivity Conference (ASC98), Palm Desert, California, September, 1998.
(5) N. Yoshikawa, Z. J. Deng, S. R. Whiteley and T. Van Duzer, "Data-Driven Self-Timed RSFQ Demultiplexer", Abstract of 1998 Applied Superconductivity Conference (ASC98), Palm Desert, California, September, 1998.
(6) L. Zheng, N. Yoshikawa, Z. J. Deng, S. R. Whiteley and T. Van Duzer, "20 GHz RSFQ Multiplexer and Demultiplexer", Abstract of 1998 Applied Superconductivity Conference (ASC98), Palm Desert, California, September, 1998.
(7) M. Jeffery, L. Zheng, N. Yoshikawa, J. Koshiyama, and T. Van Duzer, "Single-Flux-Quantum Railroads: Component Development for a 64 Gb/s Digital Superconducting Ring Data Bus", Abstract of 1998 Applied Superconductivity Conference (ASC98), Palm Desert, California, September, 1998.ｖ
1999
(1) N. Yoshikawa and J. Koshiyama, "A Cell-Based Design Apploach for RSFQ Circuits using Binary Decision Diagram", Extended Abstract of 7th International Superconductive Electronics Conference (ISEC'99), Berkeley, California, June, 1999, pp. 100-102.
(2) N. Yoshikawa and Y. Kato, "Reduction of Power Consumption of RSFQ Circuits by Inductance-Load-Biasing", Extended Abstract of 7th International Superconductive Electronics Conference (ISEC'99), Berkeley, California, June, 1999, pp. 339-341.
(3) N. Yoshikawa and K. Yoneyama, "Parameter Optimization of Single Flux Quantum Digital Circuits Based on Monte Carlo Yield Analysis", Extended Abstract of 7th International Superconductive Electronics Conference (ISEC'99), Berkeley, California, June, 1999, pp. 342-344.
(4) M. Jeffery, N. Yoshikawa, J. Koshiyama, L. Zhang and T. Van Duzer, "Component Development for a 16 Gb/s Digital Superconducting Ring Data Bus", Extended Abstract of 7th International Superconductive Electronics Conference (ISEC'99), Berkeley, California, June, 1999, pp. 45-47.
2000
(1) N. Yoshikawa, H. Kimura and M. Sugahara, "Monte-Carlo Simulation of Logic Circuits Using the Resistively Coupled Single-Electron Transistor", Abstracts of 2000 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures (QDS2000), Sapporo, Japan, September, 2000, pp.128.
(2) N. Yoshikawa and J. Koshiyama, "Top-Down RSFQ Logic Design Based on a Binary Decision Diagram", Abstract of 2000 Applied Superconductivity Conference (ASC2000), Virginia Beach, Virginia, September, 2000, pp.106.
(3) J. Koshiyama and N. Yoshikawa, "A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram", Abstract of 2000 Applied Superconductivity Conference (ASC2000), Virginia Beach, Virginia, September, 2000, pp.66.
(4) N. Yoshikawa, T. Abe, Y. Kato and H. Hoshina, "Component Development for a 16 Gb/s RSFQ-CMOS Interface System", Abstract of 2000 Applied Superconductivity Conference (ASC2000), Virginia Beach, Virginia, September, 2000, pp.90.
(5) N. Yoshikawa, "Cell-Based Top-Down Design Methodology for RSFQ Digital Circuits", Abstract of 13th International Symposium on Superconductivity (ISS2000), Tokyo, Japan, October, 2000, pp.75.
2001
(1) N. Yoshikawa, H. Miyakawa, K. Motoori, T. Van Duzer and S. Whiteley, "Josephson-CMOS Hybrid Memory Using Three-Transistor DRAM Cell", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 29-30.
(2) K. Fujiwara, J. Koshiyama and N. Yoshikawa, "Design and Test of RSFQ High-Speed Packet Switches", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 163-164.
(3) F. Matsuzaki, K. Yoda, J. Koshiyama, K. Motoori and N. Yoshikawa, "Design of small RSFQ Microprocessor based on Cell-Based Top-Down Design Methodology", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 165-166.
(4) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(5) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(6) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(7) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(8) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
(9) K. Yoda and N. Yoshikawa, "Cell-Based Design Methodology based on BDD RSFQ Logic Circuits - Tolerance of Basic Cells to Circuit Parameter Variations -", Extended Abstract of 8th International Superconductive Electronics Conference (ISEC'01), Osaka, Japan, June, 2001, pp. 167-168.
2002
(1) N. Yoshikawa, F. Matsuzaki, N. Nakajima, K. Fujiwara, K. Yoda and K. Kawasaki, "Design and Component Test of a Tiny Processor based on the SFQ Technology", Abstract of 2002 Applied Superconductivity Conference (ASC2002), Houston, Texas, August 2002, pp.24.
(2) N. Yoshikawa, K. Yoda, H. Hoshina, K. Kawasaki, K. Fujiwara, F. Matsuzaki, and N. Nakajima, "Cell Based Design Methodology for BDD SFQ Logic Circuits: a High Speed Test and Feasibility for Large Scale Circuit Applications," Abstract of 2002 Applied Superconductivity Conference (ASC2002), Houston, Texas, August 2002, pp.49.
(3) K. Fujiwara, H. Hoshina, Y. Yamashiro, N. Yoshikawa, "Design and Component Test of SFQ Shift Register Memories", Abstract of 2002 Applied Superconductivity Conference (ASC2002), Houston, Texas, August 2002, pp.16.
(4) Y.J. Feng, X. Meng, S. R. Whiteley, T. Van Duzer, K. Fujiwara, H. Miyakawa, N. Yoshikawa, "Josephson-CMOS hybrid memory with ultra-high-speed interface circuit", Abstract of 2002 Applied Superconductivity Conference (ASC2002), Houston, Texas, August 2002, pp.24.
(5) N. Yoshikawa, F. Matsuzaki, N. Nakajima, K. Fujiwara, K. Yoda and K. Kawasaki, " Design of a Tiny Microprocessor Based on the Single-Flux-Quantum Circuit Technology", Extended Abstracts of the 2002 International conference on Solid State Devices and Materials, Nagoya, September 2002, pp. 244-245.
(6) F. Matsuzaki, N. Yoshikawa, M. Tanaka, A. Fujimaki, Y. Takai, "A Behavioral-Level HDL Description of SFQ Logic Circuits for Quantitative Performance Analysis of Large-Scale SFQ Digital Systems", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 291.
(7) K. Fujiwara, H. Miyakawa, N. Yoshikawa, Y. Feng, S.R. Whiteley, T. Van Duzer, "Implementation and Low Speed Test of Ultra-Fast Interface Circuits for Josephson-CMOS Hybrid Memories", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 141.
(8) A. Fujimaki, T. Kondo, M. Tanaka, H. Hayakawa, N. Takagi, F. Matsuzaki, N. Yoshikawa, H. Terai, S. Yorozu, and Y. Takai, "Development of Single Flux-Quantum Microprocessor toward High-End Servers", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 142.
(9) S. Yorozu, Y. Kameda, Y. Hashimoto, H. Terai, a. Fujimaki, and N. Yoshikawa, "Single Flux Quantum Circuit Technology Innovation for Backbone Router Applications", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 143.
(10) H. Terai, Y. Kameda, S. Yorozu, A. Fujimaki, N. Yoshikawa and Z. Wang, "High-Speed Testing of Tandem-banyan Packet Switch Component", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 144.
(11) M. Tanaka, T. Kondo, A. Sekiya, A. Fujimaki, H. Hayakawa, F. Matsuzaki, N. Yoshikawa, H. Terai and s. Yorozu, "Component Test toward Single-flux-Quantum Processors", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 144.
(12) A. Sekiya, T. Matsumoto, M. Tanaka, A. Fujimaki, H. Hayakawa, S. Yorozu, H. Terai and N. Yoshikawa, "Measurement of bit error rate in SFQ shift register at high frequencies", Abstracts on 15th International Symposium on Superconductivity (ISS2002), Yokohama, November 2002, pp. 290.
2003
(1) K. Fujiwara, Y. Yamashiro, N. Yoshikawa, A. Fujimaki, H. Terai and S. Yorozu, "Design and High-Speed Test of 4 x 8-bit SFQ Shift Register Files," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo11.
(2) T. Hanai, T. Matsumoto, S. Yorozu, Y. Kameda, H. Terai, N. Yoshikawa, A. Fujimaki, and H. Hayakawa, "Design of the speedup buffer for the SFQ network switch, " Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo12.
(3) Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai and N. Yoshikawa, "Demonstration of passive interconnection between single-flux-quantum circuit blocks," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo13.
(4) K. Kawasaki, K. Yoda, N. Yoshikawa, A. Fujimaki, H. Terai and S. Yorozu, "Design and Implementation of a High-Speed Bit-Serial Adder Based on the Binary Decision Diagram," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo21.
(5) N. Nakajima, F. Matsuzaki, Y. Yamanashi, N. Yoshikawa, M. Tanaka, T. Kondo, A. Fujimaki, H. Terai and S. Yorozu, "Design and Implementation of Circuit Components of the SFQ Microprocessor, CORE 1," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo26.
(6) H. Terai, S. Yorozu, A. Fujimaki, N. Yoshikawa and Z. Wang, "New design approach to realize high-density SFQ circuit using multi wiring layer process," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo34.
(7) T. Van Duzer, S. R. Whiteley, X. Meng, Q. Liu and N. Yoshikawa, "High-speed interface amplifiers for SFQ-to-CMOS conversion," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo35.
(8) Y. Yamanashi, K. Kawasaki, N. Yoshikawa, H. Terai, A. Fujimaki, Y. Kameda and S. Yorozu, "A Calculation of Bias Current Distribution in Large-Scale SFQ Logic Circuits", Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo37.
(9) Y. Yamashiro, K. Fujiwara, N. Yoshikawa, N. Harada and S. Yorozu, "Bit-Error-Rate Simulation of Josephson Latching Drivers for SFQ-Semiconductor Hybrid Systems," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo38.
(10) N. Yoshikawa, K. Kawasaki, K. Yoda, A. Fujimaki, H. Terai and S. Yorozu, "20 GHz Operation of Bit-Serial Handshaking Modules for Asynchronous SFQ Logic Circuit Systems," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PMo39.
(11) M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, H. Terai, S. Yorozu, N. Yoshikawa, A. Fujimaki, and H. Hayakawa, "Prototypic Design of the Single-Flux-Quantum Microprocessor, CORE1," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, PTu38.
(12) A. Fujimaki, H. Terai, S. Yorozu, and N. Yoshikawa, "Recent SFQ research in Japan," Extended Abstract of 9th International Superconductivity Conference, 7-11 July 2003, Sydney, Australia, ITh3.
(13) N. Yoshikawa, K. Fujiwara, F. Matsuzaki, N. Nakajima, Y. Yamanashi, A. Fujimaki, M. Tanaka, T. Kondo, H. Hayakawa, H. Terai, S. Yorozu, and Y. Takai, "Development of Single-Flux-Quantum Microprocessors for Network Servers," Abstracts on 16th International Symposium on Superconductivity (ISS2003), Tsukuba, October 2003, pp.146.
(14) Y. Kameda, S. Yorozu, Y. Hashimoto, H. Terai A. Fujimaki and N. Yoshikawa, "High-speed Demonstration of Single-Flux-Quantum Cross/bar Switch up to 50 GHz," Abstracts on 16th International Symposium on Superconductivity (ISS2003), Tsukuba, October 2003, pp.147.
(15) Y. Yamanashi, M. Ito, A. Tagami and N. Yoshikawa, "High-speed Measurement Method of Quantized Energy Levels in Josephson Junctions Using SFQ Circuits," Abstracts on 16th International Symposium on Superconductivity (ISS2003), Tsukuba, October 2003, pp.315.
(16) M. Ito, N. Nakajima, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai and Yorozu, "Design and Implementation of SFQ Programmable Clock Generators," Abstracts on 16th International Symposium on Superconductivity (ISS2003), Tsukuba, October 2003, pp.318.
(17) K. Fujiwara, Y. Yamashiro, N. Yoshikawa, H. Hashimoto, S. Yorozu, H. Terai, A. Fujimaki, "High-Speed Test of SFQ-Shift Register Files with PTL Wiring," Abstracts on 16th International Symposium on Superconductivity (ISS2003), Tsukuba, October 2003, pp.322.
2004
(1) M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, A. Fujimaki, H. Hayakawa, N. Yoshikawa, H. Terai and S. Yorozu, " A Single-Flux-Quantum Logic Prototype Microprocessor", Technical Digest of IEEE International Solid-State Circuits Conference, San Francisco, USA, February, 2004, pp.298-299.
(2) A. Fujimaki, M. Tanaka, T. Kondo, T. Kawamoto, Y. Yamanashi, N. Nakajima, A. Akimoto, N. Yoshikawa, H. Terai, S. Yorozu and Y. Hashimoto"18 GHz Operation of an 8-bit Microprocessor Based on a Single-Flux-Quantum LSI Technology," Extended Abstracts of the 2004 International conference on Solid State Devices and Materials, Tokyo, September 2004, pp. 140-141.
(3) N. Yoshikawa, T. Tomida, K. Tokuda, Q. Liu, S. Whiteley and T. Van Duzer "High-Speed Digital Systems by Hybridization of CMOS and Single-Flux-Quantum Logic Circuits" Extended Abstracts of the 2004 International conference on Solid State Devices and Materials, Tokyo, September 2004, pp. 142-143.
(4) M. Tanaka, T. Kondo, T. Kawamoto, Y. Kamiya, A. Fujimaki, H. Hayakawa, Nagoya University; N. Nakajima, Y. Yamanashi, A. Akimoto, N. Yoshikawa"Demonstration of a Single-Flux-Quantum Microprocessor Using Passive Transmission Lines" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 1ES01 .
(5) S. Yorozu, Y. Kameda, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa"Progress of Single Flux Quantum Packet Switch Technology" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 1ES04 .
(6) Q. Liu, T. Van Duzer, X. Meng, S.R. Whiteley, N. Yoshikawa, "Simulation and Measurements on a 64-kbit Hybrid Josephson-CMOS Memory" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 1ES05 .
(7) Y. Kameda, S. Yorozu, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa "Single-flux-quantum (SFQ) circuit design and test of crossbar switch scheduler" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 1ES07 .
(8) K. Fujiwara, N. Nakajima, T. Nishigai, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu"Error Rate Test of Large-Scale SFQ Digital Circuit Systems" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 1ES08 .
(9) T. Yamada, M. Yoshida, T. Hanai, A. Fujimaki, H. Hayakawa, Y Kameda, S. Yorozu, H. Terai, N. Yoshikawa"Quantitative Evaluation of the Single-Flux-Quantum Cross/Bar Switch" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 2EK04 .
(10) A. Fujimaki, T. Hanai, T. Yamada, M. Yoshida, S. Yorozu, Y Kameda, H. Terai, N. Yoshikawa, "Demonstration of a Single-Flux-Quantum 2x2 Switch Prototype with Time-Shift-Speedup-Buffer" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 3EA01 .
(11) M. Ito, K. Kawasaki, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "20 GHz Operation of Bit-Serial Handshaking Systems using Asynchronous SFQ Logic Circuits" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 3EA03 .
(12) N. Yoshikawa, T. Tomida, K. Tokuda, Q. Liu, X. Meng, S.R. Whiteley, T. Van Duzer, "Characterization of 4 K CMOS Devices and Circuits for Hybrid Josephson-CMOS Systems" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 3EA06 .
(13) Y.Yamanashi, M. Ito, A. Tagami, N. Yoshikawa, "Observation of Quantized Energy Levels in a Josephson Junction Using SFQ Circuits" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 3ER01 .
(14) T. Yamada, H. Ryoki, A. Fujimaki, H. Hayakawa, Y. Hashimoto, S. Yorozu, H. Terai, N. Yoshikawa, "Experimental Analysis of Pulse Propagation in Narrowed Passive Transmission Lines" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 4EI02 .
(15) Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, N Yoshikawa,"Implementation of a 4X4 switch with passive interconnects" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 4EI06 .
(16) N. Yoshikawa, T. Nishigai, H. Kojima, K. Fujiwara, A. Fujimaki, T. Yamada, M. Tanaka, S. Yorozu, M. Hidaka, H. Terai,"Magnetic Shielding against DC Bias Current toward Large-Scale SFQ Integrated Circuits"Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 4ES05 .
(17) H. Terai, Z. Wang, Y. Hashimoto, S. Yorozu, A. Fujimaki, N. Yoshikawa, "The Relationship Between Bit-Error Rate, Operating Speed, and Circuit Scale of SFQ Circuits" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 5EJ01 .
(18) T. Nishigai, M. Ito, N. Yoshikawa, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, H. Terai, S. Yorozu, "Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram" Abstract of 2004 Applied Superconductivity Conference (ASC2004), Jacksonvill, Florida, October 2004 5EJ06 .
(19) A. Fujimaki, M. Tanaka, Y. Kamiya, T. Kawamoto, K. Takagi, N. Takagi, Y. Yamanashi, A. Akimoto, K. Fujiwara, N. Yoshikawa, H. Terai, S. Yorozu, Y. Takai, "Development of Single-Flux-Quantum Microprocessors" Abstracts on 17th International Symposium on Superconductivity (ISS2004), Niigata, November 2004, pp.322.
(20) T. Yamada, H. Ryoki, A. Fujimaki, Y. Hashimoto, S. Yorozu, H. Terai, N. Yoshikawa "Investigations of Passive Transmission Lines using Multilayerd Wireing Structure in Single-Flux-Quantum Circuits" Abstracts on 17th International Symposium on Superconductivity (ISS2004), Niigata, November 2004, pp.322.
(21) H. Kojima, Y. Yamashiro, K. Fujiwara, N. Yoshikawa,A. Fujimaki, H. Terai, S. Yorozu, "Parameter Optimization of a Josephson Latching Driver based on Bit-Error-Rate Simulations" Abstracts on 17th International Symposium on Superconductivity (ISS2004), Niigata, November 2004, pp.322.
(22) A. Akimoto, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, S. Yorozu, H. Terai, "Consideration of Logic Synthesis and Clock Distribution Networks for SFQ Logic Circuits" Abstracts on 17th International Symposium on Superconductivity (ISS2004), Niigata, November 2004, pp.322.
(23) M. Tanaka, T. Kondo, T. Kawamoto, Y. Kamiya, K. Fujiwara, Y. Yamanashi, A. Akimoto, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, "Desing of a Datapath for Single-Flux-Quantum Microprosesors with Multiple ALUs" Abstracts on 17th International Symposium on Superconductivity (ISS2004), Niigata, November 2004, pp.322.
(24) T. Nishigai, N. Yoshikawa, M. Ito, A. Fujimaki, H. Terai, S. Yorozu, "Design and Implementation of Double Oscillator Time-to-Digital Converter using SFQ Logic Circuits" Abstracts on 17th International Symposium on Superconductivity (ISS2004), Niigata, November 2004, pp.322.
2005
(1) N. Yoshikawa, Y. Yamanashi, "Measurement of Quantized Energy Levels in a Josephson Junction Using Single Flux Quantum Circuits" Proceeding of 2005 Japan-Taiwan Symposium on Superconductive Electronics, Sapporo, Hokkaido, February 2005.
(2) N. Yoshikawa, "High-Speed Integrated Systems Using Single-Flux-Quantum Circuits" 2005 Symposium on COE for Creation of Future Social Infrastructure Based on Information Telecommunication Technology in Yokohama National University, Yokohama, March 2005.
(3) N. Yoshikawa, "RSFQ and hybrid JJ-CMOS memories", US/Japan/Europe Superconductor Digital Electronics Workshop, University of California, Berkeley, May 17-18, 2005.
(4) M. Tanaka, T. Kawamoto, Y. Yamanashi, Y. Kamiya, A. Akimoto, K. Fujiwara, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, "Design of a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands,O-A01.
(5) Q. Liu, X. Meng, S. R. Whiteley, T. Van Duzer, K. Fujiwara, M. Tokuda, N. Yoshikawa"Measurements on the Josephson -CMOS Hybrid Memory" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands,O-A03.
(6) M. Tokuda, T. Tomida, H. K. Kojima, N. Yoshikawa, K. Fujiwara, Q. Liu, T. VanDuzer"Access-Time Measurements of Josephson-CMOS Hybrid Memory using SFQ Circuits", Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-B05.
(7) Y. Yamanashi, A. Akimoto, N. Yoshikawa, M. Tanaka, T. Kawamoto, Y. Kamiya, A. Fujimaki, "A New Design Approach for Control Circuits of a Pipelined Single-Flux-Quantum Microprocessor" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-B06.
(8) H. Michie, M. kidono, N. Yoshikawa, "Design of a CMOS Deceimation Filter for Josephson/CMOS Hybrid AD Converters" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-B07.
(9) H. Kojima, N. Yoshikawa, S. Yorozu, Y. Hashimoto, Y. Kameda, H. Terai, A. Fujimaki, "Bit-Error-Rate Simulation of Josephson Latching Drivers using the 10kA/cm2 Nb Process" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-I09. 発表資料
(10) K. Fujiwara, T. Hikida, N. Yoshikawa, A. Fujimaki, S. Yorozu, H. Terai, "Influence of Ground Return Current on Large-Scale SFQ Circuits", Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-I10.
(11) T. Yamada, A. Fujimaki, Y. Hashimoto, S. Yorozu, H. Terai, N. Yoshikawa, "Passive Transmission Lines Using Multilayered Wiring Structure in Single-Flux-Quantum Circuits", Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-I11.
(12) T. Nishigai, M. Ito, S. Yamada, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "Design of a Pipelined Asynchronous SFQ Microprocessor Using Handshaking Protocol" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-I12.
(13) A. Akimoto, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "Consideration of Logic Synthesis and a Clock Network for Single-Flux-Quantum Logic Circuits" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, P-I13. 発表資料
(14) S. Yorozu, Y. Hashimoto, Y. Kameda, H. Kojima, N. Yoshikawa, H. Suzuki, "Integration of a prototype cryopackage with cryocooler for large-throughput superconducting digital systems" Extended Abstract of 10th International Superconductivity Conference, 5-9 September 2005, Noord wijkerhout,The Netherlands, O-V02.
(15) H. Terai, S. Yorozu, A. Fujimaki, N. Yoshikawa, Z. Wang, "Signal integrity in larage-scale single-flux-quantum circuit" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.147.
(16) Y. Kameda, S. Yorozu, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa, "40-GHz operation of a single-flux-quantum (SFQ) switch scheduler" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.148.
(17) K. Obata, M. Tanaka, Y. Tashiro, Y. Kamiya, N. Irie, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, "Single-flux-quantum integer multiplier with systolic array structure" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.149.
(18) Y. Yamanashi, Y. Nobumori, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "Influences of global dispersion of onductances on singleflux quantum circuit operation" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.324.
(19) H. - J. Park, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, S. Yorozu, H. Terai, "Design of bit-slice adders using SFQ lofic circuits" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.326.
(20) T. Hikida, H. Kojima, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "High-density SFQ integrated circuits using josephson inductance" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.326.
(21) G. Matsuda, Y. Yamanashi, N. Yoshikawa, "Design of the microwave chopper for superconducting qubits" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.329.
(22) T. Nishigai, S. Yamada, N. Yoshikawa, "Design and imaplementation of low-power SFQ circuits using lr-load-biasing technique" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.329.
(23) Y. Yamanashi, T. Asano, N. Yoshikawa, "On-chip microwave generator for manipulation of superconductive quantum bits" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.330.
(24) S. Yorozu, Y. Hashimoto, T. Miyazaki, Y. Kameda, H. Kojima, N. Yoshikawa, H. Suzuki, "A prototype cryocooled package for large-throughput superconducting digital systems" Abstracts on 18th International Symposium on Superconcuctivity (ISS2005), Tsukuba, October 2005, pp.331.
2006
(1) Y. Hashimoto, S. Yorozu, Y. Kameda, H. Suzuki, T. Miyazaki, H. Kojima, N. Yoshikawa, “Implementation and experimental evaluation of a cryocooled system prototype for high-throughput SFQ digital applications” Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EX01
(2) M. Tanaka, Y. Kamiya, N. Irie, A. Fujimaki, Y. Yamanashi, A. Akimoto, H. Park, N. Yoshikawa, H. Terai, S. Yorozu. “ A new design approach for high-throughput arithmetic circuits for single-flux-quantum” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EB06.
(3) H. Terai, Z. Wang, M .Tanaka, A Fujimaki, Y. Yamanashi, N. Yoshikawa, Y . Hashimoto, “Diagnostic Test of Large-Scale SFQ Shift Register” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 2EI05.
(4) Q. Liu, K. Fujiwara, X. Meng, T. Van Duzer, N. Yoshikawa, Y. Thakahashi, T. Hikida, N. Kawai, “Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EB08.
(5) Y. Yamanashi, T. Nishigai, N. Yoshikawa, “Study of LR-Loading Technique for Low-Power Single Flux Quantum Circuits” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 1EX07
(6) Y. Yamanashi, A. Akimoto, H. Park, N. Yoshikawa, M. Tanaka, Y. Kamiya, N. Irie, A. Fujimaki, H Terai, S. Yorozu, “Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1b” Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 3EY01
(7) H. Park, Y. Yamanashi, N .Yoshikawa, A. Fujimaki, M. Tanaka, H. Terai, S. Yorozu, “Design of Bit-Slice Adders Using RSFQ Logic Circuits” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 3EY03.
(8) G. Matsuda, Y. Yamanashi, N. Yoshikawa, “Design of an SFQ Microwave Chopper for Controlling Quantum Bits” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 1EX05.
(9) T. Hikida, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, NICT; S. Yorozu, “Bit-Error-Rate Measurements of RSFQ Shift Register Memories” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EB05.
(10) Y. Takahashi, M. Tokuda, N. Kawai, N. Yoshikawa, K. Fujiwara, Q. Liu, T. Van Duzer, “Access-Time Measurements of a Josephson-CMOS Hybrid Memory using an RSFQ Time-to-Digital Converter” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 2EI03.
(11) Y. Nobumori, T. Nishigai, K. Nakamiya, N. Yoshikawa, A. Fujimaki, H. Terai, NICT; S. Yorozu, “Design and Implementation of a Fully Asynchronous RSFQ Microprocessor: SCRAM2” Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 3EY02.
(12) A. Fujimaki, M. Tanaka, N. Irie, S. Iwasaki, T. Yamada, N. Takagi, H. Park, Y. Yamanashi, N. Yoshikawa, H. Terai, S. Yorozu, Y. Takai, “Development of High-speed Single-flux-quantum Microprocessors,” Abstracts on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 160
(13) S. Iwasaki, M. Tanaka, N. Irie, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, “Quantative Evaluation of Delay Time in the Single-flux-Quantum Circuits,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 161
(14) Y. Yamanashi, N. Yoshikawa, “Study on a DC-powered On-chip Voltage Generator Using SFQ Circuits,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 329.
(15) T. Hikida, T. Nishigai, N. Yoshikawa, “Consideration of Low-power SFQ Circuits Using Josephson-junction-load Biasing,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 331.
(16) K. Churei, H. Kojima, N. Yoshikawa, Y. Hashimoto, Y. Kameda, S. Yorozu, “Bit-error-rate Simulations of Josephson Latching Drivers Using the 10kA/cm2Nb Process,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 332.
(17) K. Nakamiya, T. Nishigai, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, “Improvement of Time Resolution of the Double-Oscillator Time-to-digital Converter Using SFQ Circuits.” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 333.
(18) N. Kawai, N. Yoshikawa, “Reduction of a Bit-error-rate of Josephson Latching Drivers Using Series Inductors,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 334.
2007
(1) K. Nakamiya, N. Yoshikawa, A. Fujimaki, Y. Hashimoto, H. Terai, “Demonstration of picosecond delay time measurements by single-flux-quantum double-oscillator time-to-digital converters,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, O-A03.
(2) N. Kawai, Y. Takahashi, K. Gotoh, N. Yoshikawa, T. Van Duzer, “Characterization of 90 nm Cryo-CMOS Devices and Circuits for Hybrid Josephson-CMOS Memories,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, P-B01.
(3) S. Iwasaki, M. Tanaka, Y. Yamanashi, H. Park, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, H. Honda, K. Inoue, “Design of a reconfigurable data-path prototype in the single-flux-quantum circuit,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, P-B02.
(4) Y. Yamanashi, H. Park, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi, “Design and Implementation of Single-Flux-Quantum Floating-Point Adders,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, P-B03.
(5) M. Tanaka, Y. Yamanashi, N. Irie, H. -J. Park, S. Iwasaki, K. Takagi, K. Taketomi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, “Design and implementation of a pipelined 8-bit-serial single-flux-quantum microprocessor with cache memories,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, P-B04.
(6) Y. Kameda, Y. Hashimoto, S. Yorozu, H. Terai, A. Fujimaki, N. Yoshikawa, M. Hidaka, S. Nagasawa, K. Hinode, T. Sato, “4x4 SFQ network switch prototype system demonstration and 10-Gbps bit-error-rate test,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, P-B06.
(7) K. Churei, N. Yoshikawa, S. Yorozu, Y. Hashimoto, “Parameter Optimization of Josephson Latching Drivers using Bit-Error-Rate Simulations,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, P-B09.
(8) N. Yoshikawa, M. Tanaka, Y. Yamanashi, N. Irie, H. Park, S. Iwasaki, K. Taketomi, A. Fujimaki, H. Terai, S. Yorozu, “(Invited) Review of the CORE1 Microprocessor Project: Recent Development and Next Plans,” Extended Abstract of 11th International Superconductivity Electronics Conference, 10-14 June 2007, Washington DC, USA, I-S01.
(9) K. Fujiwara, Q. Liu, X. Meng, T. Van Duzer, N. Yoshikawa, “Half-Nanosecond Latency Measurement on a 64-kbit Josephson-CMOS Memory,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, O-S01.
(10) N. Irie, M. Tanaka, Y. Yamanashi, H. -J. Park, N. Yoshikawa, H. Terai, S. Yorozu, A. Fujimaki, “Scalable Cache Memory for a Bit-Serial Single-Flux-Quantum Microprocessor,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, O-S02.
(11) H. Hara, Y. Nobumori, N. Yoshikawa, A. Fujimaki, Y. Hashimoto, H. Terai, “Asynchronous High-Speed Operation of RSFQ First-In First-Out Buffers,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, O-S03.
(12) H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi, “Fast Bit-Serial Multipliers Using RSFQ Logic Circuits,” Extended Abstract of 11th International Superconductivity Conference, 10-14 June 2007, Washington DC, USA, O-S04.
(13) K. Taketomi, Y. Yamanashi, H. Park, N. Yoshikawa, A. Fujimaki, Y. Hashimoto, H. Terai, “Design and High-speed Test of a Multiplier Accumulator for Fast Fourier Transforming Using SFQ Circuits,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FD-6, pp. 136.
(14) M. Igarashi, K. Churei, N. Yoshikawa, K. Fujiwara, Y. Hashimoto, “D Flip-Flop Based Pulse Transfer Circuits for Current Recycling,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FD-7, pp. 137.
(15) H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, K. Fujiwara, N. Takagi, “Multifunctional Buffers Using SFQ Logic Circuits,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FDP-73, pp. 325.
(16) N. Kawai, Y. Takahashi, N. Yoshikawa, T.V. Duzer, “Access Time Measurement of 16-kb Josephson-CMOS Hybrid Memories Using RSFQ Time-to-Digital Converters,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FDP-74, pp. 325.
(17) K. Nakamiya, N. Yoshikawa, “Demonstration of Picosecond Delay Time Measurements of the High-Speed Signal from The Room Temperature by Single-Flux-Quantum Double-Oscillator Time-To-Digital Converters,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FDP-75, pp. 326.
(18) H. Hara, Y. Yamanashi, H. Park, K. Churei, K. Nakamiya, M. Igarashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, Y. Hashimoto, H. Terai, “Examination of Bias-Current Shielding Structure of SFQ Logic Cells for The Large Circuit Yield,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FDP-76, pp. 326.
(19) K. Churei, N. Yoshikawa, Y. Hashimoto “Parameter Optimization and BER Measurement of Josephson Latching Drivers Using The 10 kA/cm2 Nb Process,” Abstracts on 20th International Symposium on Superconductivity (ISS2007), Tsukuba, November 2007, FDP-78, pp. 327.
(20) N. Yoshikawa, “(Invited) Superconductor Electronics based on Single-Flux-Quantum Circuit Technology,” East Asia Symposium on Superconductor Electronics (EASSE2007), 11-15 December 2007, Delhi, India.
2008
(1) Y. Hashimoto, S. Nagasawa, T. Satoh, K. Hinode, H. Suzuki, T. Miyazaki, M. Hidaka, N. Yoshikawa, H. Terai, A. Fujimaki, “Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System Demonstration,” Technical Digest, 2008 IEEE International Solid-State Circuit Conference (ISSCC2008), San Francisco, Feb. 3-7, 2008, pp. 532-533.
(2) S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa, “New Nb multi-layer Fabrication Process for Superconducting SFQ VLSI Circuits,” Superconducting SFQ VLSI Workshop 2008, A1-1, Yokohama National University, Japan, Mar. 2008.
(3) I. Kataeva, S. Iwasaki, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, “Demonstration of the key components of an SFQ Reconfigurable Data-Paths Processor: an Operand Routing Network and a 2×2 RDP prototype,” Superconducting SFQ VLSI Workshop 2008, I2, Yokohama National University, Japan, Mar. 2008.
(4) M. Tanaka, K. Obata, Y. Yamanashi, H. Park, S. Iwasaki, K. Taketomi, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, “CORE1: Review and Recent Developments in Bit-serial SFQ Microprocessors,” Superconducting SFQ VLSI Workshop 2008, I3, Yokohama National University, Japan, Mar. 2008.
(5) N. Yoshikawa, “Development of SFQ Logic Gated with Passive Transmission lines and Their Application to Digital Signal Processors,” Superconducting SFQ VLSI Workshop 2008, A2-1, Yokohama National University, Japan, Mar. 2008.
(6) H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi, “Design and Implementation of the SFQ Floating Point Units,” Superconducting SFQ VLSI Workshop 2008, A2-5, Yokohama National University, Japan, Mar. 2008.
(7) H. Suzuki and N. Yoshikawa, “Design of SFQ logic cells connected directly to PTLs,” Superconducting SFQ VLSI Workshop 2008, P2-4, Yokohama National University, Japan, Mar. 2008.
(8) K. Kondo, Y. Yamanashi, H. Park, N. Yoshikawa, “Delay Elements for Passive Transmission Lines Using Josephson Inductance,” Superconducting SFQ VLSI Workshop 2008, P2-5, Yokohama National University, Japan, Mar. 2008.
(9) M. Igarashi, N. Yoshikawa, K. Fujiwara, Y. Hashimoto, “SFQ Pulse Transfer Circuits Using Inductive Coupling for Current Recycling,” Superconducting SFQ VLSI Workshop 2008, P2-6, Yokohama National University, Japan, Mar. 2008.
(10) Y. Saito, Y. Yamanashi, N. Yoshikawa, “Development of Short-Line-Width On-Chip Microwave Generators for Controlling Superconducting Qubits,” Superconducting SFQ VLSI Workshop 2008, P2-7, Yokohama National University, Japan, Mar. 2008.
(11) Y. Natsume, M. Igarashi, K. Churei, N. Yoshikawa, “High Density Integration of SFQ Shift Register Memories using Phase Quantum Logic Circuits,” Superconducting SFQ VLSI Workshop 2008, P2-8, Yokohama National University, Japan, Mar. 2008.
(12) H. Park, Y. Yamanashi, H. Hara, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi, “Design and Implementation of the SFQ Half-Precision Floating Point Adder,” Superconducting SFQ VLSI Workshop 2008, P2-9, Yokohama National University, Japan, Mar. 2008.
(13) H. Hara, K. Obata, H. Park, Y. Yamanashi, N. Yoshikawa, M. Tanaka, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi, “Design and Implement of SFQ Half-Precision the Floating-Point Multiplier,” Superconducting SFQ VLSI Workshop 2008, P2-10, Yokohama National University, Japan, Mar. 2008.
(14) H. Jin, N. Kawai, Y. Okamoto, N. Yoshikawa, “Access Time Measurement of Josephson-CMOS Hybrid Memories using SFQ Time-to-Digital Converter,” Superconducting SFQ VLSI Workshop 2008, P2-11, Yokohama National University, Japan, Mar. 2008.
(15) K. Taketomi, Y. Yamanashi, H. Park, and N. Yoshikawa, “Design and Implementation of the Butterfly Processing Unit for FFT processor using Rapid Single Flux Quantum Circuit,” Superconducting SFQ VLSI Workshop 2008, P2-12, Yokohama National University, Japan, Mar. 2008.
(16) N. Yoshikawa, “(Invited) RSFQ projects in Japan,” 5th FLUXONICS RSFQ design workshop, June 2008, Ilmenau.
(17) N. Yoshikawa, “(Invited) Advanced aspects of VLSI design,” 5th FLUXONICS RSFQ design workshop, June 2008, Ilmenau.
(18) A. Fujimaki, S. Iwasaki, K. Takagi, R. Kasagi, I. Kataeva, H. Akaike, M. Tanaka, N. Takagi, N. Yoshikawa, K. Murakami, “(Invited) Demonstration of an SFQ-Based Accelerator Prototype for a High-Performance Computer,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EZ01.
(19) H. Hara, H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, K. Obata, M. Tanaka, N. Takagi, K. Takagi, A. Fujimaki, S. Nagasawa, “Design and Implementation of SFQ Half-Precision Floating-Point Multipliers,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EZ03.
(20) M. Igarashi, K. Churei, N. Yoshikawa, K. Fujiwara, Y. Hashimoto, “SFQ pulse transfer circuits using inductive coupling for current recycling,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 4EB06.
(21) I. Kataeva, H. Akaike, A. Fujimaki, N. Takagi, N. Yoshikawa, K. Inoue, H. Honda, K. Murakami, “An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EZ07.
(22) H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa, “(Invited) Design and Implementation of SFQ Half-Precision Floating-Point Adders,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 4EB01.
(23) T. Satoh, K. Hinode, S. Nagasawa, Y. Kitagawa, M. Hidaka, N. Yoshikawa, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, “Multi-layer Nb Integrated Circuit Structure Incorporating the Top Active Layer,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EPB04.
(24) K. Taketomi, Y. Yamanashi, H. Park, N. Yoshikawa, A. Fujimaki, Y. Hashimoto, H. Terai, “Design and High-Speed Test of a Radix-2 Butterfly Unit for the Fast Fourier Transform Using SFQ Circuits,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EZ06.
(25) M. Tanaka, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, “A high-throughput single-flux-quantum floating-point serial divider using the signed-digit representation,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EZ02.
(26) Y. Yamanashi, N. Yoshikawa, T. Van Duzer, “A Novel Power Line to Reduce the Magnetic Field of Supply Currents in Josephson Digital Circuits,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 2EPB05.
(27) Y. Yamanashi, N. Yoshikawa, ” Superconductive Random Number Generator Using Thermal Noises in SFQ Circuits,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 3EPC07.
(28) N. Yoshikawa, K. Nakamiya, ” Demonstration of picosecond-delay measurements of high-speed signals by single-flux-quantum double-oscillator time-to-digital converters,” 2008 Applied Superconductivity Conference (ASC 2008), August 2008, Chicago, 1EB05.
(29) S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, N. Yoshikawa, “New Nb multi-layer fabrication process for large-scale SFQ circuits,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FD-22-INV.
(30) N. Yoshikawa, H. Park, H. Hara, K. Taketomi, Y. Yamanashi, I. Kataeva, R. Kasagi, S. Iwasaki, H. Akaike, A. Fujimaki, M. Tanaka, K. Obata, Y. Ito, K. Takagi, N. Takagi, H. Honda, K. Inoue, K. Murakami, S. Nagasawa, M. Hidaka, “(Invited) Recent development of Large-Scale reconfigurable data-paths using RSFQ Circuits,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FD-25-INV.
(31) H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, A. Fujimaki, K. Takagi, M. Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, M. Hidaka, N. Takagi, “SFQ cell design for A Nb-10-layer process,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FDP-20.
(32) Y. Natsume, M. Igarashi, Y. Yamanashi, N. Yoshikawa, “High-density integration of single-flux-quantum circuits using Josephson inductance,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FDP-21.
(33) I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, “An operand routing network for an SFQ-RDP processor: new design and experimental results,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FDP-22.
(34) H. Suzuki, H. Hara, Y. Yamanashi, N. Yoshikawa, “Design of SFQ circuits based on gate-to-gate wiring using passive transmission lines,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FDP-23.
(35) K. Taketomi, Y. Yamanashi, H.J. Park, N. Yoshikawa, A. Fujimaki, H. Terai, “Design and implementation of a butterfly unit with memories for fast Fourier transforming using SFQ circuits,” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FDP-24.
(36) N. Takeuchi, Y. Yamanashi, Y. Saito, N. Yoshikawa, “3D simulation of superconducting microwave devices with an electromagneticfield simulator” Abstracts on 21st International Symposium on Superconductivity (ISS2008), Tsukuba, October 2008, FDP-46.
(37) N. Yoshikawa, “(Invited) SFQ time-to-digital converters,” 2nd panel discussion on standardization in superconducting electronics, Tsukuba, October 2008.
(38) N. Takeuchi, Y. Saitoh, Y. Yamanashi, N. Yoshikawa, “Design of RSFQ microwave choppers for controlling Josephson junction qubits,” Proceeding of 2008 International symposium on Physics of Quantum Technology, Nara, November 2008, p.105.
(39) Y. Saitoh, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, “Implementation and low temperature tests of RSFQ microwave choppers or controlling Josephson junction qubit,” Proceeding of 2008 International symposium on Physics of Quantum Technology, Nara, November 2008, p.106.
2009
(1) M. Tanaka, K. Takagi, N. Takagi,Y. Yamanashi, N. Yoshikawa, “High-Throughput Arithmetic Circuits based on Systolic Architecture for SFQ Reconfigurable Data-Path,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, O4.
(2) I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, “A Crossbar Switch for Routing of 2-bit Wide Data Streams,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, O5.
(3) Y. Natsume, M. Igarashi, Y. Yamanashi, N. Yoshikawa, “Numerical Simulation of Magnetic Shielding Effect in Superconducting Shield Structures,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P1.
(4) N. Takeuchi, H. Suzuki, Y. Yamanashi, N. Yoshikawa, “Design of Miniaturized Superconducting Passive Delay Lines for RSFQ Circuits,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P4.
(5) T. Kainuma, H. Suzuki, Y. Yamanashi, N. Yoshikawa, M. Tanaka, A. Fujimaki, “Evaluation of Logic-Level Simulation using the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P8.
(6) D. Ozawa, Y. Natsume, Y. Yamanashi, N. Yoshikawa, “Investigation of Multi-Flux Drivers using High-bc Junctions,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P9.
(7) H. Jin, Y. Okamoto, K. Yaguchi, Y. Yamanashi, N. Yoshikawa, “Investigation of Characteristic Variations of Wholly CMOS Amplifiers for Josephson/CMOS Hybrid Memories,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P10.
(8) K. Yaguchi, Y. Okamoto, H. Jin, H. Park, Y. Yamanashi, N. Yoshikawa, T. Van Duzer, “Implementation of a Self-Bias Circuit for Josephson-CMOS Hybrid Memories,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P11.
(9) W.H. Kim, Y. Yamanashi, K. Taketomi, H.J. Park, T. Kainuma, N. Yoshikawa, “Implementation of a User Interface System for SFQ Microprocessors,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 15, 2009, P13.
(10) N. Yoshikawa, “(Invited) Recent Research Activities in the MEXT SFQ Project,” Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), Kyushu University School of Medicine, Fukuoka, June 16, 2009, June 2009, I4.
(11) A. Fujimaki, R. Kasagi, K. Takagi, I. Kataeva, H. Akaike, M. Tanaka, N. Takagi, N. Yoshikawa, K. Murakami, “(invited) Demonstration of 2x3 Reconfigurable-data-path Processors with 14000 Josephson Junctions,” Technical Program of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 17, 2009, SP-O4.
(12) Y. Yamanashi, T. Kainuma, M. Igarashi, H. Hara, K. Taketomi, H. Park, H. Suzuki, Y.Natsume, N. Yoshikawa, H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, M. Itoh, A.Fujimaki, S. Nagasawa, M. Hidaka, “100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 17, 2009, SP-O6.
(13) I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, K. Takagi, N. Takagi, K. Murakami, “Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP-P12.
(14) H. Akaike, M. Tanaka, K. Takagi, I. Kataeva, R. Kasagi, M. Itoh, A. Fujimaki, M. Igarashi, H. Park, Y. Yamanashi, N. Yoshikawa, K. Fujiwara, S. Nagasawa, T. Satoh, M. Hidaka, K. Takagi, N. Takagi, “Single-flux-quantum Cells and Circuits Based on a Nb Multi-layer Process,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP-P13.
(15) Y. Yamanashi, T. V. Duzer, N. Yoshikawa, “New Design to Show the Advantage of a Twisted-Pair Bias Supply Line for Large-Scale Josephson Circuits,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP-P16.
(16) H. Park, T. V. Duzer, Q. Liu, S. R. Whiteley, Y. Okamoto, Y. Yamanashi, D. Wei, N. Yoshikawa, “Improvements of Josephson-CMOS Hybrid Memory System,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP- P17.
(17) T. Sugiura, Y. Yamanashi, N. Yoshikawa, “Statistical Evaluation of a Superconductive Physical Random Number Generator,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP-P18.
(18) Y. Natsume, M. Igarashi, D. Ozawa, Y. Yamanashi, N. Yoshikawa, “High-Density Integration of Single-Flux-Quantum Circuits using Josephson Inductance,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP-P25.
(19) H. Suzuki, H. Hara, Y. Yamanashi, N. Yoshikawa, “Design of SFQ Circuits using PTL-connectable Logic Cells,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 18, 2009, SP-P26.
(20) N. Takeuchi, Y. Saito, Y. Yamanashi, N. Yoshikawa, “Design and Implementation of RSFQ Microwave Choppers for Controlling JosephsonJunction Qubits,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 19, 2009, SP-P35.
(21) S. Nagasawa, T. Satoh, K. Hinode, Y. Kitagawa, M. Hidaka, H. Akaike, A. Fujimaki, N. Takagi, K. Takagi, N. Yoshikawa, “(Invited) Nb Multi-layer Device Fabrication Technology,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 19, 2009, SP-P36.
(22) Y. Okamoto, H. Park, H. Jin, K. Yaguchi, Y. Yamanashi, N. Yoshikawa, T. V. Duzer, “Access Time Measurements of Josephson/CMOS Hybrid Memories using SFQ Delay Measurement Circuits,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 19, 2009, SP-P39.
(23) T. Kainuma, H. Park, K. Taketomi, H. Hara, Y. Yananashi, N. Yoshikawa, M. Tanaka, Y. Ito, A. Fujimaki, N. Takagi, K. Takagi,S. Nagasawa, “Design and High-speed Tests of Component Circuits of an SFQ Half-precision Floating-point Adder using 10 kA/cm2 Nb Process,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 19, 2009, SP-P43.
(24) N. Yoshikawa, H. Suzuki, H. Hara, A. Murakami, Y. Yamanashi, “(Invited) Design of SFQ Multi-Stop Time-to-Digital Converters for Time-of-Flight Mass Spectrometry,” Extended Abstract of International Superconductive Electronics Conference 2009 (ISEC 2009), Kyushu University School of Medicine, Fukuoka, June 19, 2009, SP-P44.
(25) N. Yoshikawa, H. Park, H. Hara, Y. Yamanashi, A. Fujimaki, K. Takagi, N. Takagi, M. Hidaka, “(Invited) Recent Developments in Floating-Point Processors using Single-Flux-Quantum Circuits,” 9th European Conference on Applied Superconductivity (EUCAS 2009), Dresden, Germany, September 15, 2009.
(26) N. Yoshikawa, T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi and K. Takagi, “(Invited) Component Design and Test of 50-GHz Half-Precision Floating-Point Adders and Multipliers,” EUROFLUX 2009 International Conference, Avignon, France, September 22, 2009.
(27) T. Kainuma, H. Park, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, “Design of Component Circuits of an SFQ Half-Precision Floating-Point Adder using 10 kA/cm2 Nb Process,” Abstracts on 22nd International Symposium on Superconductivity (ISS2009), Tsukuba, October 4, 2009, FDP-44.
(28) N. Takeuchi, D. Ozawa, Y. Yamanashi, N. Yoshikawa, “On-Chip RSFQ Microwave Pulse Generator for Controlling Superconducting Qubits,” Abstracts on 22nd International Symposium on Superconductivity (ISS2009), Tsukuba, October 4, 2009, FDP-45.
(29) N. Yoshikawa,T. Kainuma, H. Park, Y. Yamanashi, A. Fujimaki, N. Takagi and K. Takagi, “(Invited) High-Speed Floating-Point Processors based on Single-Flux-Quantum Circuit Technology,” Asian Conference of Applied Superconductivity and Cryogenics (ACASC 2009), Matsue, Japan, December 7, 2009.
2010
(1) N. Yoshikawa, H. Suzuki, K. Taketomi, and Y. Yamanashi, “Development of SFQ Logic Gates Connectable to Passive Transmission Lines and Their Application to Digital Signal Processors,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, A02-2, pp.16-20.
(2) T. Sugiura, Y. Yamanashi, and N. Yoshikawa, “Demonstration of 30 GHz generation of truly random numbers using superconductive circuit,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P1, pp.38-40.
(3) Y. Yamanashi, I. Okawa, and N. Yoshikawa, “Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Circuits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P3, pp.45-46.
(4) D. Ozawa, Y. Natsume, Y. Yamanashi, and N. Yoshikawa, “Design and Evaluation of Multi-Flux Drivers Using High b鐶 Junctions,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P4, pp.47-48.
(5) T. Xue, P. Heejoung, Y. Yamanashi, and N. Yoshikawa, “Effect of Parasitic Inductance and Capacitance on the Stability of Josephson Latching Drivers,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P6, pp.51-52.
(6) K. Minami, Y. Yamanashi, and N. Yoshikawa, “Design of a single-flux quantum majority logic gate,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P9, pp.59-60.
(7) T. Shimojima, Y. Yamanashi, and N. Yoshikawa, “Consideration of a digital SQUID with positive magnetic feedback,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P10, pp.61-62.
(8) Y. Natsume, D. Ozawa, Y. Yamanashi, and N. Yoshikawa, “SFQ Chip-to-Chip Communication using Inductive Coupling,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P11, pp.63-64.
(9) H. Suzuki, Y. Yamanashi, and N. Yoshikawa, “Design of a 2 x 2 switch using PTL-connectable logic cells,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P12, pp.65-66.
(10) Y. Okamoto, H. Park, H. Jin, K. Yaguchi, Y. Yamanashi, N. Yoshikawa, and T. Van Duzer, “Access Time Measurement of 64 kb Josephson/CMOS Hybrid Memories by using SFQ Time-to-Digital Converter,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P13, pp.67-70.
(11) Y. Takahashi, H. Suzuki, Y. Yamanashi, and N. Yoshikawa, “Design of Input Circuits for SFQ Multi-Stop Time-to-Digital Converters for Time-of-Flight Mass Spectrometry,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P14, pp.71-72.
(12) S. Miura, N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Improvement of SFQ Circuit Systems for Measuring Escape Rates of Josephson Junctions,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P20, pp.86-88.
(13) N. Takeuchi, D. Ozawa, S. Miura, Y. Yamanashi, and Y. Yoshikawa, “Design of RSFQ Circuits for Controlling Superconducting Quantum Bits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P21, pp.89-94.
(14) Y. Arita, Y. Yamanashi, T. Baba, and N. Yoshikawa, “Integrating optical waveguides with SFQ circuits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13 , 2010, P22, pp.95-97.
(15) T. Kainuma, F. Miyaoka, Y. Shimamura, Y. Yamanashi, and N. Yoshikawa, “Proposal of Resettable Muller-C gates Using Single-Flux-Quantum Circuits,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P23, pp.98-99.
(16) K. Yaguchi, Y. Okamoto, H. Jin, H. Park, Y. Yamanashi, N. Yoshikawa, and T. Van Duzer, "Implementation of a Self-Bias Circuit for Josephson-CMOS Hybrid Memories" Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P24, pp.100-102.
(17) H. Jin, Y. Okamoto, H. Park, K. Yaguchi, Y. Yamanashi, and N. Yoshikawa, “Investigation of High-Speed CMOS Differential Amplifier for Josephson/CMOS Hybrid Memory Systems,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P27, pp.107-108.
(18) Y. Shimamura, T. Kainuma, F. Miyaoka, H. Park, Y. Yamanashi, and N. Yoshikawa, “Design of an SFQ Half-Precision Floating-Point Multipliers Using 10 kA/cm2 Nb Multi- Layer Process,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2010), Yokohama National University, Yokohama, January 13, 2010, P28, pp.109-110.
(19) M. Tanaka, H. Akaike, A. Fujimaki, Y. Yamanashi, N. Yoshikawa, S. Nagasawa, K. Takagi, and N. Takagi, “100-GHz single-flux-quantum bit-serial adder based on 10-ka/cm2 niobium process,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 4, 2010, 3EY-01.
(20) Y. Shimamura, K. Toshiki, F. Miyaoka, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, and K. Takagi, “50 GHz operation of SFQ floating-point multiplier using 10 kA/cm^2 Nb process,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-01.
(21) N. Yoshikawa, and D. Ozawa “Adiabatic quantum flux parametron as an ultra-low-power superconducting logic device,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 4, 2010, 3EB-06.
(22) T. Sugiura, Y. Yamanashi, and N. Yoshikawa, “Demonstration of 30 Gbit/s generation of superconductive true random number generator,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-04.
(23) T. Kainuma, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, and K. Takagi, “Design and implementation of component circuits of an SFQ half-precision floating-point adder using 10 kA/cm2 Nb process,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-06.
(24) D. Ozawa, Y. Natsume, Y. Yamanashi, and N. Yoshikawa, “Design and Implementation of Multi-flux drivers using High Beta_c Junctions,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-01.
(25) Y. Yamanashi, I. Okawa, and N. Yoshikawa, “Design approach of dynamically reconfigurable single flux quantum logic gates,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-07.
(26) F. Miyaoka, T. Kainuma, Y. Shimamura, Y. Yamanashi, and N. Yoshikawa, “High-speed test of a radix-2 butterfly processing element for the Fast Fourier Transform using SFQ circuits,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EY-05.
(27) K. Yaguchi, Y. Okamoto, H. Jin, H. Park, Y. Yamanashi, N. Yoshikawa, and T. Van Duzer, “Implementation of Josephson-CMOS hybrid memories with bit-serial data input/output ports,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-02.
(28) Y. Arita, N. Yoshikawa, T. Baba, and Y. Yamanashi, “Integration of optical waveguides with SFQ circuits,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-03.
(29) H. Jin, Y. Okamoto, K. Yaguchi, Y. Yamanashi, and N. Yoshikawa, “Investigation of characteristic variations of high-speed cryo CMOS amplifiers for interface circuits of the Josephson/CMOS hybrid memories,” 2010 Applied Superconductivity Conference (ASC 2010), Washington DC, USA, Aug 5, 2010, 4EPA-05.
2011
(1) N. Yoshikawa, “Overview of the hybrid memory project at YNU,” Superconducting electronics meeting at Berkeley, University of California at Berkeley, May 18-20, 2011.
(2) K. Kuwabara amd N. Yoshikawa, “Design of 8-T SRAM cells and improvement of Josephson latching drivers,” Superconducting electronics meeting at Berkeley, University of California at Berkeley, May 18-20, 2011.
(3) J. Hyun-Joo and N. Yoshikawa, “Development of CMOS amplifiers for Josephson-CMOS interface,” Superconducting electronics meeting at Berkeley, University of California at Berkeley, May 18-20, 2011.
(4) N. Yoshikawa, “Ultra-low-power computing using adiabatic QFP,” Superconducting electronics meeting at Berkeley, University of California at Berkeley, May 18-20, 2011.
(5) M. Okada, I. Kataeva, M. Tanaka, H. Akaike, A. Fujimaki, N. Yoshikawa, S. Nagasawa, N. Takagi, “(Invited)45 GHz operation of Single-Flux-Quantum Reconfigurable Data-Path Processor with 11000 Josephson Junctions,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EB-I2.
(6) Masamitsu Tanaka, Shota Takeshima, Kazuyoshi Takagi, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Shuichi Nagasawa, Naofumi Takagi, “Multi-Layered Single-Flux-Quantum Circuits Designed Using Timing-Driven Automatic Routing,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EB-O7.
(7) Y. Shimamura, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, “Design and implementation of SFQ Floating-Point Multiplier and Adder Using 10 kA/cm2 Nb Process,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EB-O8.
(8) Tomoya Imaizumi, Yuki Yamanashi, Nobuyuki Yoshikawa, Thomas Ortlepp, ” Single Flux Quantum Comparator: A study of Gray Zone Width and Operation Frequency in dependence on circuit parameters,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EA-P12.
(9) Y. Shimamura, N. Yoshikawa, T. Ortlepp, “Analysis of computational energy efficiency in single flux quantum electronics by implementing an integer-based hardware-algorithm,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EA-P15.
(10) K. Suzuki, M. Ukibe, S. Shiki, S. Miki, Z. Wang, Y. Takahashi, N. Yoshikawa, M. Ohkubo, “Pulse height distribution analysis for superconducting nanostripline ion detector with fast pulse-integration analog-to-digital converter,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EA-P49.
(11) Y. Takahashi, Y. Yamanashi, N. Yoshikawa, S. Miki, Z. Wang, K.Suzuki, M. Ukibe, M. Ohkubo, “Design and Implementation of SFQ Multi-Stop Time-to-Digital Converters for Time-of-Flight Mass Spectrometry,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 19, 2011, 1-EA-P50.
(12) N. Yoshikawa, F. Miyaoka, K. Hinago, Y. Shimamura, Y. Yamanashi, “100-GHz high-speed demonstration of circuit components of FFT processors using 10 kA/cm2 Nb process,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 20, 2011, 2-EA-O15.
(13) N. Yoshikawa, D. Ozawa, Y. Yamanashi, “Circuit demonstration of ultra-low-power adiabatic quantum flux parametrons,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 20, 2011, 2-EB-O5.
(14) Yuki Yamanashi, Tatsuro Sugiura, Nobuyuki Yoshikawa, “Novel Superconductive Physical Random Number Generator Using Timing Jitter in Single Flux Quantum Circuit,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 20, 2011, 2-EA-P13.
(15) K. Ehara, Y. Yamanashi, N. Yoshikawa, “Investigation of bias-current-supply methods for serially biased SFQ circuits,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 20, 2011, 2-EA-P15.
(16) H. Jin, K. Yaguchi, Y. Yamanashi, N. Yoshikawa, “Investigation of Robust CMOS Amplifiers for Josephson-CMOS Hybrid Memories,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 20, 2011, 2-EA-P17.
(17) S. Miura, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Implementation of SFQ Microwave Choppers for Controlling Quantum Bits,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 20, 2011, 2-EA-P26.
(18) Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi, “Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 22, 2011, 4-EA-P14.
(19) H. Jin, K. Yaguchi, Y. Yamanashi, N. Yoshikawa, T. V. Duzer, “Access Time Measurement of Josephson-CMOS Hybrid Memory Systems with an SFQ Bit-Serial Data-Input Port,” International Superconductivity Electronics Conference (ISEC2011), Hague, Netherlands, September 22, 2011, 4-EA-P16.
(20) N. Yoshikawa, “(Invited)Margin and Energy Consumption of Adiabatic QFP Logic,” 7th FLUXONICS RSFQ design workshop 2011, Ilmenau, Germany, September 26, 2011.
(21) Y. Shimamura, N. Yoshikawa, Y. Yamanashi, “SFQ Logic Cells Directly Connectable to Passive Transmission Lines,” 7th FLUXONICS RSFQ design workshop 2011, Ilmenau, Germany, September 27, 2011.
(22) K. Ehara, N. Yoshikawa, Y. Yamanashi, “Current Recycling Technique for SFQ Circuits,” 7th FLUXONICS RSFQ design workshop 2011, Ilmenau, Germany, September 27, 2011.
(23) H. Jin, N. Yoshikawa, Y. Yamanashi, “High-Speed CMOS Amplifiers for Josephson-CMOS Interfaces,” 7th FLUXONICS RSFQ design workshop 2011, Ilmenau, Germany, September 27, 2011.
(24) N. Yoshikawa, D. Ozawa, Y. Yamanashi, “Ultra-Low-Power Superconducting Logic Devices using Adiabatic Quantum Flux Parametron,” Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM 2011), Nagoya, September 30, 2011, J-8-3.
(25) N. Yoshikawa, K. Ehara, K. Inoue, Y. Yamanashi, “Investigaation of Rpbustness of Logic Gates using Ultra-Low-Power adiavatic Quantum Flux Parametron,” Abstracts on 24nd International Symposium on Superconductivity (ISS2011), Tokyo, October26 , 2011, FD-15.
(26) Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa, “Comparison of 3D-electromagnetic simulation methods for designing superconductor microwave devices,” The 6th East Asia Symposium on Superconductor Electronics (EASSE 2011), Yamagata University, Yonezawa, October 27, 2011, 27-P-20.
(27) Nobuyuki Yoshikawa, Kohei Ehara, Kenta Inoue, Naoki Takeuchi, Yuki Yamanashi, “Development of Ultra-Low-Power Processors Using Adiabatic Quantum-Flux-Parametron Logic,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2011), Kyoto Research Park, Kyoto, November 1, 2011, O-1.
(28) Nobuyuki Yoshikawa, “(Invited) Energy-efficient logic circuits using adiabatic quantum flux parametron,” The 6th East Asia Symposium on Superconductor Electronics (EASSE 2011), Yamagata University, Yonezawa, October 28, 2011, 28-DH-2
(29) Yuto Tsuga, Yuki Yamanashi, Nobuyuki Yoshikawa, “Development of an asynchronous digital SQUID magnetometer,” The 6th East Asia Symposium on Superconductor Electronics (EASSE 2011), Yamagata University, Yonezawa, October 27, 2011, 27-P-07
(30) Kazuki Aoki, Yuki Yamanashi, Nobuyuki Yoshikawa, “Time division multiplexing for a multi-channel asynchronous digital SQUID system,” The 6th East Asia Symposium on Superconductor Electronics (EASSE 2011), Yamagata University, Yonezawa, October 27, 2011, 27-P-08.
(31) Shogo Miura, Yuki Yamanashi, Nobuyuki Yoshikawa, “High-speed escape-rate measurements of Josephson junctions using SFQ circuits,” The 6th East Asia Symposium on Superconductor Electronics (EASSE 2011), Yamagata University, Yonezawa, October 27, 2011, 27-P-11.
2012
(1) N. Yoshikawa, "(Invited) Ultra-low-power superconducting logic using adiabatic quantum flux parametrons: What is the minimum energy dissipation in computation?," Laboratory for Physical Sciences Seminar, College Park, U.S.A., March 7, 2012.
(2) N. Yoshikawa, K. Ehara, K. Inoue, N. Takeuchi and Y. Yamanashi, “(Invited) Experimental Demonstration of Ultra-Low-Power Adiabatic Quantum-Flux-Parametron Logic,” International Conference on Superconductivity and Magnetism (ICSM2012), Istanbul, Turkey, April 29 May 4, 2012.
(3) N. Yoshikawa, “(Invited) Ultra-Low-Power, Robust Superconducting Logic using Adiabatic Quantum Flux Parametrons,” 11th International Symposium on High Temperature Superconductors in High Frequency Fields (HTSHFF 2012), May 29, 2012, Matsushima, Miyagi, Japan.
(4) K. Aoki, Y. Yamanashi, N. Yoshikawa, “Multiplexing Techniques of Single Flux Quantum Circuit Based Readout Circuit for a Multi-Channel Sensing System,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October 11, 2012, 4EB-03.
(5) M. Dorojevets, C.L. Ayala, N. Yoshikawa, A. Fujimaki, “16-bit wave-pipelined sparse-tree RSFQ adder: a new generation of superconductor circuits,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EE-03.
(6) M. Dorojevets, C.L. Ayala, N. Yoshikawa, A. Fujimaki, “8-bit asynchronous sparse-tree superconductor RSFQ arithmetic logic unit with a rich set of integer operations,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 2EPA-04 .
(7) M. Dorojevets, A.K. Kasperek, N. Yoshikawa, A. Fujimaki, “8x8-bit parallel carry-save superconductor RSFQ multiplier,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EE-02 .
(8) Y. Tsuga, Y. Yamanashi, N. Yoshikawa, “Asynchronous Digital SQUID Magnetometer with an On-Chip Magnetic Feedback for Improvement of Magnetic Resolution,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 4EB-05.
(9) N. Yoshikawa, Y. Takahashi, K. Sano, Y. Yamanashi, M. Okubo, K. Suzuki, N. Zen, M. Koike, S. Miki, Z. Wang, “(Invited) Demonstration of single-flux-quantum readout circuits for time-of-flight mass spectrometry of biomolecules using superconducting nano-stripline detectors,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 4EF-01.
(10) K. Hinago, Y. Yamanashi, N. Yoshikawa, “ Design and component development of DC-powered single-flux-quantum random-access memories using vortex transition memory cells,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EA-01.
(11) K. Kuwabara, H. Jin, Y. Yamanashi, N. Yoshikawa, “Design and demonstration of 64-kb Josephson-CMOS hybrid memories,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 1EPR-04 .
(12) T. Mukaiyama, Y. Yamanashi, N. Yoshikawa, “Design and demonstration of energy-recoverable on-chip AC power sources for adiabatic quantum-flux-parametron circuits,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 1EPR-05.
(13) A. Fujimaki, M. Okada, M. Tanaka, H. Akaike, S. Nagasawa, N. Yoshikawa, K. Murakami, N. Takagi, “Design and demonstration of high-speed RSFQ processors with large-scale reconfigurable data paths,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EE-01.
(14) H. Jin, K. Kuwabara, Y. Yamanashi, N. Yoshikawa, “Development of high-sensitive CMOS differential amplifiers for SFQ digital readout circuits,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 1EPR-03.
(15) K. Ehara, A. Takahashi, Y. Yamanashi, N. Yoshikawa, “Development of pulse transfer circuits for serially biased SFQ circuits using the Nb 9-layer 1-μm process,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EE-06 .
(16) H. Honda, F. Mehdipour, N. Yoshikawa, H. Kataoka, K. Inoue, A. Fujimaki, N. Takagi, K.J. Murakami, “Evaluating Performance of Scientific Applications Realized on a Single-Flux Quantum-Based Accelerator,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EE-05.
(17) M. Otsubo, Y. Yamanashi, N. Yoshikawa, “Improvement of Operation Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October 9, 2012, 2EPA-05.
(18) S. Hachiya, Y. Yamanashi, N. Yoshikawa, “Improvement of Performance of a Superconductive Random Number Generator by On-Chip Data Processing,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 2EPA-08.
(19) N. Takeuchi, K. Ehara, K. Inoue, Y. Yamanashi, N. Yoshikawa, “Margins and energy dissipation of adiabatic quantum-flux-parametron logic at finite temperature,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 2EPA-07.
(20) N. Takeuchi, K. Ehara, K. Inoue, Y. Yamanashi, N. Yoshikawa, “Measurement of 40-zJ energy dissipation of adiabatic quantum-flux-parametron logic using a superconducting resonator,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 2EE-07.
(21) X. Peng, Y. Yamanashi, N. Yoshikawa, “Optimization of the structure and circuit parameters of Josephson latching drivers for Josephson/CMOS hybrid memories,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 3EA-05.
(22) Y. Yamanashi, K. Umeda, N. Yoshikawa, “Pseudo Sigmoid Function Generator for a Superconductive Neural Network,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 2EPA-06.
(23) K. Inoue, K. Ehara, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Simulation and experimental demonstration of logic circuits using ultra-low-power adiabatic quantum-flux-parametron,” 2012 Applied Superconductivity Conference (ASC 2012), Portland, Oregon, USA, October, 2012, 2EE-03.
(24) N. Yoshikawa, “DC-powered single-flux-quantum random-access memories using vortex transition memory cells,” Post ASC’12 Workshop on 4 K Random Access Memory, Berkeley, California, USA, October 14-15, 2012.
(25) N. Yoshikawa, “Present status and perspective of Josephson-CMOS hybrid memories,” Post ASC’12 Workshop on 4 K Random Access Memory, Berkeley, California, USA, October 14-15, 2012.
(26) N. Yoshikawa, “Recent Research Development on Adiabatic Quantum-Flux Parametron as Ultra-Low-Power Logic,” Proceedings of Superconducting SFQ VLSI Workshop (SSV 2012), Nagoya University, Nagoya, December 7, 2012, SO-2.
2013
(1) X. Peng, Y. Shimamura, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa, "(Invited) Design and High-Speed Demonstration of SFQ Bit-Serial Floating-Point Multipliers Using ISTEC 10 kA/cm2 Nb Process, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, A3.
(2) N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Novel Latch for Adiabatic Quantum-Flux-Parametron Logic, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, A5.
(3) Coenrad J. Fourie, X. Peng, A. Takahashi, N. Yoshikawa,"Modelling and calibration of ADP process for inductance calculation with InductEx, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA4.
(4) K. Inoue, N. Takeuchi, K. Ehara, Y. Yamanashi, N. Yoshikawa "Simulation and implementation of an 8-bit carry look-ahead adder using adiabatic quantum-flux-parametron logic, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA7.
(5) T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa, "60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm2 Nb Process," International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA8.
(6) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, "Energy Dissipation and Bit-Error-Rate of Adiabatic Quantum-Flux-Parametron Logic with Under-Damped Junctions," International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA17.
(7) Q. Xu, Y. Shimamura, N. Yoshikawa, T. Ortlepp, "High-speed demonstration of an integer-based hardware-algorithm using energy-efficient single-flux-quantum circuits,"
(8) International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA22.
(9) A. Takahashi, Y. Yamanashi, N. Yoshikawa, "High-speed measurement of serially biased large-scale SFQ circuits, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PA26.
(10) F. China, Y. Yamanashi, N. Yoshikawa, "New superconductive digital magnetometer with sub-flux quantum resolution, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PB1.
(11) K. Sato, Y. Yamanashi, N. Yoshikawa, "Novel multiple input single flux quantum merge circuit using serially connected dc-SQUIDs, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PB4.
(12) Y. Yamanashi, Y. Tsuga, N. Yoshikawa, "Magnetic field tolerant single-flux-quantum circuit for superconducting sensing system, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PB6.
(13) K. Sano, A. Takahashi, Y. Yamanashi, N. Yoshikawa, N. Zen, K. Suzuki, M. Ohkubo, "Design and High-Speed Tests of a Single-Flux-Quantum Time-to-Digital Converter for Time-of-Flight Mass Spectrometry, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, D3.
(14) X. Peng, Y. Sasaki, H. Jin, K. Kuwabara, Y. Yamanashi, N. Yoshikawa, "Demonstration of Fully Functional 64-kb Josephson/CMOS Hybrid Memory," International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, H1.
(15) A. Fujimaki, N. Yoshikawa, M. Hidaka, "Research Trend of Superconductor Digital Electronics in Japan, " International Superconductive Electronics Conference (ISEC2013), Cambridge, USA, July 8, 2013, PL1.
(16) X. Peng, H.Suzuki, Y.Yamanashi, N. Yoshikawa, "A Method to Provide Bias Current for Large-Scale SFQ Circuitsusing Locally Isolated Ground Planes" European Conference on Applied Superconductivity (Eucas2013), Genova, Italy, September 17, 2013, 2P-EL2-02.
(17) N. Takeuchi, Y. Ymanashi, N. Yoshikawa, "Purely reversible quantum-flux-parametron logic," European Conference on Applied Superconductivity (Eucas2013), Genova, Italy, September 17, 2013, 2M-EL-03.
(18) N. Yoshikawa, N. Takeuchi, K. Inoue and Y. Yamanashi, "Sub-kBT Bit-Energy Operation of Superconducting Logic Devices using Adiabatic Quantum Flux ParametronExtended," Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM 2013), Fukuoka, Japan, September 24-27, 2013, E-4-1.
(19) N. Yoshikawa, N. Takeuchi, K. Inoue and Y. Yamanashi, "(Invited) Recent Developments on Ultra-Low-Energy Adiabatic Quantum-Flux-Parametron Logic,"26th International Symposium on Superconductivity (ISS 2013), Tokyo, Japan, November 18-20, 2013, FD-12-INV.
(20) K. Sano, Y. Yamanashi, N. Yoshikawa, "Study on the Reduction of the Jitter of an Signe-Flux-Quantum Time-To-Digital Converter for Time-of-Flight Mass Spectrometry," 26th International Symposium on Superconductivity (ISS 2013), Tokyo, Japan, November 18-20, 2013, FD-19.
(21) N. Takeuchi, T. Ortlepp, K. Inoue, Y. Yamanashi, N. Yoshikawa, "Proposal and Implementation of High-Speed Test Circuits for Adiabatic Quantum-Flux-Parametron Gates,"26th International Symposium on Superconductivity (ISS2013),Tokyo,Japan,
(22) November 18-20, 2013, FDP-32.
(23) D. Si, N. Takeuchi, K.Inoue, Y. Yamanashi, N. Yoshikawa, "Yield Analysis of Large-Scase Adiabatic-Quantum-Flux-Parametron Logic:The Effect of the Distribution of the Critical Current," 26th International Symposium on Superconductivity (ISS2013), Tokyo, Japan, November 18-20, 2013, FDP-33.
(24) N. Yoshikawa, "Sub-KBT Bit-Energy Operation of Superconducting Logic: What is the Minimum Energy Bound in the Computation?," East Asia Symposium on Superconductor Electronics (EASSE2013), Taiwan Normal University, Taipei, October 23-26, 2013.
(25) Y. Yamanashi, R. Tsutsumi, N. Yoshikawa, "Circuit Design of Zero-Static Power SFQ Circuit Using Magnetic Flux Biasing," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, O-3.
(26) N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Several Applications Using Quantum-Flux-Latches," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, O-4.
(27) K. Sato, Y. Yamanashi, N. Yoshikawa, "Design and Implementation of a High Sensitive DC/SFQ Converter," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-3.
(28) X. Peng, Y.Sasaki, Y. Yamanashi, N. Yoshikawa, "Improvement of Interface Circuit for Josephson/CMOS Hybrid Memories toward Ground-Current Reduction and Low Power Dissipation," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-4.
(29) S. Nishimoto, Y. Yamanashi, N. Yoshikawa, "New Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-5.
(30) S. Hachiya, Y. Yamanashi, N. Yoshikawa, "Improvement of Performance of a Superconductive Random Number Generator by Optimization of Parameters," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-7.
(31) F. China, Y. Yamanashi, N. Yoshikawa, "Improvement of Slew Rate High-Sensitive Superconductive Digital Magnetomerter ," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-8.
(32) Q. Xu, Y. Yamanashi, N. Yoshikawa, T. Ortlepp, "Imprementation of an Integer-based Hardware-Algorithm in Single-Flux-Quantum Electronics," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-9.
(33) K. Inoue, N. Takeuchi,Y. Yamanashi, N. Yoshikawa, "Design and Test of Basic Cells for Adiabatic Quantum-Flux-Parametron Logic with Magnetic-Shielding Structures," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-10.
(34) Y. Sakashita, Y. Yamanashi, N. Yoshikawa, "Design of an SFQ Butterfly Ciecuit for Signed Number Operation Using the Nb 10 kA/cm2 Josephson Process," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-11.
(35) Y. Sasaki, X. Pen, T. Nishimura, Y. Yamanashi, N. Yoshikawa, "Improvement of Decoders and Data Divers in Terms of Power Consumption for 64-kb SFQ/CMOS Hybrid Memories," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-12.
(36) Y. Muramatsu, K. Sano, Y. Yamanashi, N. Yoshikawa, "Development of Single-Flux-Quantum Multi-Threshold Current Discriminators for m/z-Sensitive Time-of-Flight Mass Spectrometry," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-13.
(37) A. Takahashi, Y. Yamanashi, N. Yoshikawa, "Evaluation of Serially Biased SFQ Circuits Using Floating Ground Plane Structures," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-15.
(38) R. Numaguchi, A. Takahashi, Y. Yamanashi, N. Yoshikawa, "Development of Low-Power Shift-Register Memories Using Josephson-Junction-Biasing SFQ Circuits," Superconducting SFQ VLSI Workshop (SSV2013), Tsukuba, Japan, November 21-22, 2013, P-18.
2014
(1) N. Yoshikawa, “(Invited lecture) Adiabatic Superconducting Circuits and Reversible Computing,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, L-4.
(2) Y. Komura, M. Tanaka, A. Fujimaki, N. Yoshikawa, S. Nagasawa, “Study on Latching Driver with Enlarged Operating Margin for Josephson RAM,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, O-3.
(3) K. Sano, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Evaluation of a Single-Flux-Quantum Time-to-Digital Converter for Time-of-Flight Mass Spectrometry in Cryo-cooler,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, O-10.
(4) R. Kihara, Y. Yamanashi, N. Yoshikawa, “Evaluation of Stochastic Resonance Phenomenon in Rf-SQUID,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, O-11.
(5) X. Peng, Y. Yamanashi, N. Yoshikawa, “High-Speed Demonstration of Single-Precision Bit-Serial Floating-Point Multipliers Using Single-Flux-Quantum Circuits,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-2.
(6) Q. Xu, Y. Yamanashi, N. Yoshikawa, T. Ortlepp, “Demonstration of an SFQ-Based Bit-Serial Computing for Integer Iteration Algorithms,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-4.
(7) Y. Sakashita, T. Kato, Y. Yamanashi, N. Yoshikawa, “Design and High-Speed Operation of an Integer-Type SFQ Butterfly Circuit Using the Nb 10 kA/cm2 Josephson Process,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-6.
(8) Z. Gao, A. Takahashi, R. Numaguchi, S. Miyanishi, Y. Yamanashi, H. Suzuki, N. Yoshikawa, “Simulation and Measurement of the Vortex Transition Memory Cells for Single-Flux-Quantum Random Access Memories,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-7.
(9) R. Numaguchi, A. Takahashi, Y. Yamanashi, N. Yoshikawa, “Development of Low-Power 1k-bit Shift-Register Memories Using LR-Biasing SFQ Circuits,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-10.
(10) T. Nishimura, Y. Sasaki, X. Peng, Y. Yamanashi, N. Yoshikawa, “Development of High-Sensitive CMOS Amplifiers for Josephson-CMOS Interfaces,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-11.
(11) R. Tsusumi, Y. Yamanashi, N. Yoshikawa, “Design and Measurement of Zero-Static-Power SFQ Circuit Using Dc Magnetic Flux Biasing,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-13.
(12) S. Nishimoto, Y. Yamanashi, N. Yoshikawa, “Design of Reconfigurable Adder/Subtractor Using Dynamically Reconfigurable Single Flux Quantum DFF/NOT Gate,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-15.
(13) K. Sato, Y. Yamanashi, N. Yoshikawa, “High Speed Test of a Multiple Input Merger Using a Magnetically Coupled Dc-SQUID Stack,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-16.
(14) Y. Muramatsu, K. Sano, Y. Yamanashi, N. Yoshikawa, “Design of m/z-Sensitive Time-of-Flight Mass Spectrometry Systems Using Single-Flux-Quantum Multi-Threshold Current Discriminators,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-19.
(15) F. China, Y. Yamanashi, N. Yoshikawa, “Improvement of Dynamic Range of High-Sensitive Superconductive Digital Magnetometer,” Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS), Nagoya, Japan, March 5-7, 2014, P-21.
(16) Y. Sakashita, Y. Yamanashi, N. Yoshikawa, “75-GHz operation of an SFQ butterfly processing unit for FFT processors using the Nb 10 kA/cm2 Josephson process,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 1EOr1A- 04.
(17) X. Peng, Y. Sasaki, Y. Yamanashi, N. Yoshikawa, “Improvement of 64-kb Josephson-CMOS hybrid memories toward their complete operation,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 1EOr3A-05.
(18) S. Nishimoto, Y. Yamanashi, N. Yoshikawa, “Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 2EPo2D-05.
(19) C. J. Fourie, X. Peng, R. Numaguchi, N. Yoshikawa, “Inductance and coupling of stacked vias in a multilayer superconductive IC process,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 2EPo2D-07.
(20) X. Peng, T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa, “(Invited) High-speed demonstration of bit-serial floating-point adders and multipliers using single-flux-quantum (SFQ) circuits,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 2EOr2C-0
(21) N. Yoshikawa, K. Inoue, N. Takeuchi, Y. Yamanashi, “Design and demonstration of an 8-bit carry look-ahead adder using ultra-low-power adiabatic quantum-flux-parametron logic,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 2EOr2C-05.
(22) Y. Yamanashi, R. Tsutumi, N. Yoshikawa, “Zero Static Power Single Flux Quantum Circuit Using Magnetic Flux Biasing,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 2EOr2C-06.
(23) T. Ortlepp, M. Fiedler, N. Takeuchi, N. Yoshikawa, “Ballistic interconnects for energy efficient superconductor electronics,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 3EPo2B-06.
(24) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Experimental demonstration of logical and physical reversibility of reversible quantum-flux-parametron gates,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 3EPo2B-07.
(25) N. Zen, M. Ohkubo, S. Shiki, M. Ukibe, M. Koike, K. Sano, N. Yoshikawa, “(Invited) Dynamics of parallel superconducting strip ion detectors,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 3EPo2D-01.
(26) K. Sano, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Demonstration of Single-Flux-Quantum Time-to-Digital Converters for Time-of-Flight Mass Spectrometry,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 4EOr2A-01.
(27) Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Demonstration of a bit-serial SFQ-based computing for integer iteration algorithms,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 4EOr3A-02.
(28) K. Sato, Y. Yamanashi, N. Yoshikawa, “High Speed Operation of Single Flux Quantum Multiple Input Merger Using a Magnetically Coupled SQUID Stack,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 4EOr3A-04.
(29) N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Experimental demonstration of quantum-flux-latch-based circuits,” 2014 Appl. Superconductivity Conference (ASC 2014), Charlotte, North Carolina, USA, August, 2014, 4EOr3A-05.
(30) N. Yoshikawa, “Superconductive Electronics Research at Yokohama National University,” 1st Stellenbosch Workshop on Superconductive Circuit Modelling and Layout Extraction, Stellenbosch, South Africa, September 1-2, 2014.
(31) N. Yoshikawa, “Design challenges for realizing large-scale single-flux-quantum circuits: how to cope with large bias currents,” 1st Stellenbosch Workshop on Superconductive Circuit Modelling and Layout Extraction, Stellenbosch, South Africa, September 1-2, 2014.
(32) Y. Yamanashi, R. Tsutsumi, N.Yoshikawa, “Design and Test of dc-Biased Zero Static Power Single Flux Quantum Circuit,” 27th International Symposium on Superconductivity (ISS2014), Tokyo, Japan, November 25-27, 2014, FD-12.
(33) K. Sano, Y. Muramatsu, T. Shimoda, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo,“Time-of-Flight Mass Spectrometry Using Signe-Flux-Quantum Time-to-Digital Converter and a Superconducting Strip Ion Detector in a Cryo-Cooler,” 27th International Symposium on Superconductivity (ISS2014), Tokyo, Japan, November 25-27, 2014, FD-18.
(34) R. Kihara, Y. Yamanashi, N. Yoshikawa, “Power Reduction of Rf-SQUID Memory Cell Using Stochastic Resonance,” 27th International Symposium on Superconductivity (ISS2014), Tokyo, Japan, November 25-27, 2014, FDP-24.
(35) F. China, Y. Yamanashi, N. Yoshikawa, “Performance Estimation and Design of High-Sensitive Superconductive Digital Magnetometer,” 27th International Symposium on Superconductivity (ISS2014), Tokyo, Japan, November 25-27, 2014, FDP-25.
(36) Q. Xu, X. Peng, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “High-speed Demonstration of an SFQ-based Computing System for Solving 3n+1 Problem,” 27th International Symposium on Superconductivity (ISS2014), Tokyo, Japan, November 25-27, 2014, FDP-28.
(37) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Adiabatic Quantum-flux-parametron Cell Library with Minimalist Design,” 27th International Symposium on Superconductivity (ISS2014), Tokyo, Japan, November 25-27, 2014,FDP-29.
(38) H. Sugata, Y. Yamanashi, N. Yoshikawa, “ Investigation of Post-Processing Circuit to Improve Superconducting Physical Random Number Generator,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-1.
(39) Q. Xu, T. Ortlepp, Y. Yamanashi, N .Yoshikawa, “High-speed Demonstration of Bit-serial SFQ-based Computing for Integer Iteration Algorithms,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-4.
(40) Y. Komura, M. Tanaka, A. Fujimaki , N. Yoshikawa, S. Nagasawa, “Development of Vortex Transition Memory Cells for a Josephson RAM,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, p-6.
(41) K. Sano, Y. Muramatsu, T. Shimoda, Y. Yamanashi, N. Yoshikawa , N. Zen, M. Ohkubo,“Demonstration of a Single-Flux-Quantum Time-to-Digital Converter with 3×24-Bit First-In First-Out Buffers for Time-of-Flight Mass Spectrometry of Biomolecules,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-9
(42) Y. Muramatsu, K. Sano, T. Shimoda, Y. Yamanashi, N. Yoshikawa, “Measurement of a Gray Zone Width of SFQ Multi-Threshold Current Discriminators for m/z-Sensitive Time-of-Flight Mass Spectrometry,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-10.
(43) Shimoda, Y. Muramatsu, K. Sano, Y. Yamanashi, N. Yoshikawa, “Comparison of Jitter in Three Types of SFQ Ring Oscillators,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-11.
(44) R. Numaguchi, T. Takahashi, N. Yoshikawa, Y. Yamanashi, A. Fujimaki, M. Tanaka, N. Takagi, K. Takagi, “Design of Shift-Register Memories for SFQ Microprocessors CORE e,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-12.
(45) T. Takahashi, R. Numaguchi, Y. Yamanashi, N. Yoshikawa, “Design of a High-Throughput Decoder for SFQ Shift-Register Memories,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-13.
(46) T. Narama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Demonstration of a 10,000-gate AQFP Circuit with 5 mA Bias Current,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, P-20.
(47) Y. Yamanashi, K. Masubuchi, N. Yoshikawa, “Statistical Analysis of the Relationship between Timing Margin and the Error Rate of Single-Flux-Quantum Logic Circuits,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, O-4.
(48) Y. Sakashita, Y. Yamanashi, N. Yoshikawa, “Investigation on Component Circuits for the SFQ FFT Processor using the 10 kA/cm2 Nb Process,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, O-7.
(49) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Recent Progress Towards a Reversible Computer using Adiabatic Superconductor Logic,” 7th Superconducting SFQ VLSI Workshop (SSV 2014), Kobe, Japan, December 1-2, 2014, O-8.
2015
(1) N. Yoshikawa, “(keynote) Ultra-energy-efficient adiabatic superconducting logic: what is the minimum energy limit in computation?”, 2015 Joint UK-Japan Workshop on Physics and Applications of Superconductivity, University of Cambridge, Cambridge, UK, April 12-15, 2015.
(2) T. Ono, Y. Yamanashi , N. Yoshikawa, “Design of a Complex Event Detector Circuit for Complex Event Processing System Using SFQ Circuits,” Superconducting SFQ VLSI Workshop (SSV 2015), Nagoya, JAPAN, July 10, 2015, Oral-4.
(3) C. L. Ayala, N. Takeuchi, Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Towards VLSI Adiabatic Quantum-Flux-Parametron Logic Circuits,” Superconducting SFQ VLSI Workshop (SSV 2015), Nagoya, JAPAN, July 10, 2015, SS-2.
(4) T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi , N. Yoshikawa, “(Invited) Demonstration of 10k gate-scale adiabatic-quantumflux-parametron circuits,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P04-INV.
(5) Y. Sakashita, T. Ono, Y. Yamanashi1, N. Yoshikawa, “Design and High-Speed Component Tests of an SFQ FFT Processor using the 10 kA/cm2 Advanced Process,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-O03.
(6) K. Sano, Y. Muramatsu, T. Shimoda, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Demonstration of a Superconducting Time-of-Flight Mass Spectrometry System Operated in a Cryo- Cooler,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DR-O07.
(7) M. Tanaka, K. Takata, R. Sato, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa, N. Zen, M. Ohkubo, “(Invited) Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-O01-INV.
(8) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Adiabatic Quantum-Flux-Parametron Cell Library with Minimalist Design and Symmetric Layout,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-O06.
(9) F. China, T. Ortlepp, T. Narama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Study of Signal Interface between Single Flux Quantum Circuit and Adiabatic Quantum Flux Parametron,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P28.
(10) N. Tsuji, N. Takeuchi, T. Narama, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Magnetically Coupled Quantum Flux Latch with Large Bias Margins,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P29.
(11) Y. Sasaki, G. Konno, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Improvement of energy efficiency of 64-kb Josephson-CMOS hybrid memories,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P30.
(12) T. Ortlepp, N. Takeuchi, C. Ayala, J. Stark, Y. Yamanashi, N. Yoshikawa,“Performance Analysis of the Adiabatic Quantum Flux Parametron in terms of Sensitivity, Speed and Power Dissipation,” International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P37.
(13) N. Takeuchi , Y. Yamanashi , N. Yoshikawa, “Energy Efficiency of Adiabatic Quantum-FluxParametron Logic”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P09.
(14) C. J. Fourie , S. Miyanishi , N. Yoshikawa, “Grounding Methods to Reduce Stray Coupling in Multi-Layer Layouts”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P15.
(15) H. Sugata , Y. Yamanashi , N. Yoshikawa, “New Random Number Generation System by Combining Superconducting Physical- and PseudoRandom Number Generators”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P16.
(16) Q. Xu , C. L. Ayala , N. Takeuchi , Y. Yamanashi , N. Yoshikawa , T. Ortlepp, “Design of Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P21.
(17) Y. Yamanashi , S. Nishimoto , N. Yoshikawa, “Single-Flux-Quantum Arithmetic Logic Unit Using Dynamically Reconfigurable Logic Gate”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P23.
(18) H. Suzuki , X. Peng , N. Yoshikawa, “Investigation of Reducing Harmful Effect of Bias Return Current on Ground Plane in Superconducting Integrated Circuits”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P24.
(19) R. Kihara , Y. Yamanashi , N. Yoshikawa, “Power Reduction of Josephson Random Access Memory Using Stochastic Resonance”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P25.
(20) R. Tsutsumi , K. Sato , Y. Yamanashi , N. Yoshikawa, “Improvement of Operation Speed of LR-Biased LowPower Single Flux Quantum Circuits by Introduction of Dynamic Resetting of Bias Currents”, International Superconductive Electronics Conference (ISEC2015), Nagoya, JAPAN, July 6-9, 2015, DS-P26.
(21) C. Ayala, N. Takeuchi, Q. XU, T. Narama, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “A Timing and Energy Extraction Approach for Logic Simulation of VLSI Adiabatic Quantum-Flux-Parametron Circuits”, European Conference on Applied Superconductivity(EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 2M-E-O1.
(22) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Study on energy dissipation in adiabatic quantum-flux-parametron logic at finite temperature”, European Conference on Applied Superconductivity(EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 3A-E-P-01.
(23) Q. XU, C. Ayala, N. Takeuchi, T. Ortlepp, N. Yoshikawa, “Creation of a Logic Simulation Model for Adiabatic Quantum Flux Parametron Logic”, European Conference on Applied Superconductivity(EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 3A-E-P-01.
(24) K. Sano, T. Shimoda, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Demonstration and Improvement of Superconducting Time-of-Flight Mass Spectrometry Systems Operated in a Cryo-Cooler”, European Conference on Applied Superconductivity (EUCAS2015), Lyon, FRANCE, September 6-10, 2015, 3A-E-P-05.
(25) N. Yoshikawa, “(Invited) SFQ readout circuits for TOF MS systems: Present status and future directions”, Workshop on readout electronics for radiation and particle detectors, Erfurt, Germany, December 20-22, 2015.
(26) T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi , N. Yoshikawa, “Demonstration of 10k gate-scale adiabatic-quantumflux-parametron circuits,” International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383438
(27) Y. Sakashita, T. Ono, Y. Yamanashi1, N. Yoshikawa, “Design and High-Speed Component Tests of an SFQ FFT Processor using the 10 kA/cm2 Advanced Process,” IEEE Trans.I nternational Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383442
(28) Q. Xu , C. L. Ayala , N. Takeuchi , Y. Yamanashi , N. Yoshikawa , T. Ortlepp, “Design of Extremely Energy-Efficient Hardware Algorithm Using Adiabatic Superconductor Logic”, IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383446
(29) M. Tanaka, K. Takata, R. Sato, A. Fujimaki, T. Kawaguchi, Y. Ando, K. Takagi, N. Takagi, N. Yoshikawa, N. Zen, M. Ohkubo, “Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories,” IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383449
(30) C. J. Fourie , S. Miyanishi , N. Yoshikawa, “Grounding Methods to Reduce Stray Coupling in Multi-Layer Layouts”, IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015, . DOI : 10.1109/ISEC.2015.7383461
(31) Y. Sasaki, G. Konno, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Improvement of energy efficiency of 64-kb Josephson-CMOS hybrid memories,” , IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383463
(32) F. China, T. Ortlepp, T. Narama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, T. Ortlepp “Study of Signal Interface between Single Flux Quantum Circuit and Adiabatic Quantum Flux Parametron,” IEEE Trans. International Superconductive Electronics Conference (ISEC2015) [Proceeding], Nagoya, JAPAN, July 6-9, 2015,. DOI : 10.1109/ISEC.2015.7383483
2016
(1) C. L. Ayala, N. Takeuchi, T. Ortlepp, Y. Yamanashi and N. Yoshikawa, “Kogge-Stone and Brent-Kung Adders Optimized for Adiabatic Quantum-Flux-Parametron Majority Logic”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, O-1.
(2) (Invited) N. Takeuchi, C. L. Ayala, Q. Xu, F. China, N. Tsuji, T. Ando, Y. Murai, K. Fang, Y. Yamanashi, N. Yoshikawa and T. Ortlepp, “A Review of Current Progress of Adiabatic Quantum-Flux-Parametron Logic”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, I-4.
(3) T. Ando, N. Tsuji, F. China, N. Takeuchi , S. Nagasawa, M. Hidaka, Y. Yamanashi and N. Yoshikawa, “First Demonstration of Double-Active-Layered AQFP Circuits Using Double Gate Process”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, O-7.
(4) T. Ono, H. Suzuki, Y. Yamanashi and N. Yoshikawa, “Design and Demonstration of Component Circuits for an SFQ-Based Single-Chip FFT
(5) Processor”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-2."
(6) Y. Murai, C. Ayala, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, “Towards VLSI Design and Development of AQFP EDA Software Considering 1 mm Wire Limitation”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-3.
(7) R. Sato, T. Ono, Y. Yamanashi and N. Yoshikawa, “50 GHz Demonstration of a Complex Event Detector Unit for Complex Event Processing
(8) Systems Using the Nb 10 kA/cm2 Josephson Process”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-5.
(9) K. Sano, Y. Abe, Y. Yamanashi and N. Yoshikawa, “Reduction of supply current and capacity enlargement of first-in first-out buffers in single-flux-quantum time-to-digital converters”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-6.
(10) T. Wakamatsu, Y. Yamanashi and N. Yoshikawa, “Analysis of Influences of Thermal Noises on Performance of Superconductiv Σ-Δ A/D Converter”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-7.
(11) K. Fang, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "Proposal of multi-logic-stage AQFP circuits”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-9.
(12) S. Kobako, Y. Yamanashi and N. Yoshikawa, "Design of Adiabatic-Quantum-Flux-Parametron Autocorrelator for Submillimeter-Wave Spectrometry”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-10.
(13) Q. Xu, C. L. Ayala, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "HDL-Based Cell Library for AQFP Logic Using 4-Phase Clock”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-11.
(14) T. Igarashi, H. Suzuki, Y. Yamanashi and N. Yoshikawa, "Design and Evaluation of Unipolar VTM Cell and Superconductor Loop Drivers”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-12.
(15) Y. Abe, K. Sano, Y. Yamanashi and N. Yoshikawa, "Experimental Evaluation of Josephson Comparators for Small Current Detection”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-13.
(16) H. Takayama, N. Tsuji N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "Proposal of a Random Access Memory Cell Composed of Quantum Flux Parametron”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-15.
(17) G. Konno, Y. Yamanashi and N. Yoshikawa, "Demonstration of 64-kb Josephson-CMOS Hybrid Memories with SFQ Inputs and Outputs”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-16.
(18) F. China, N. Tsuji, N. Takeuchi , T. Ortlepp, Y. Yamanashi and N. Yoshikawa, "Demonstration of Data Transmission on Long Interconnections between Adiabatic Quantum-Flux-Parametron Gates Using Passive Transmission Lines”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-17.
(19) N. Tsuji, C. Ayala, N. Takeuchi, T. Ortlepp, Y. Yamanashi and N. Yoshikawa, "Design and Implementation of an 8-Word by 1-Bit Register File Using Adiabatic Quantum Flux Parametron Logic”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-19
(20) H. Imai, Y. Yamanashi and N. Yoshikawa, "Simulation and Measurement of Influence of Flux Quantum Trapped in Moat on Superconducting Integrated Circuit”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-20
(21) T. Matsushima, T. Ortlepp, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, "Investigation of Gray Zone Width of Adiabatic Quantum Flux Parametron”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-22
(22) S. Muramatsu, Y. Yamanashi and N. Yoshikawa, "Study on Superconductive Associative Memory”, Superconducting SFQ VLSI Workshop (SSV 2016), Yokohama National University,Yokohama, August 2-3, 2016, P-23
(23) (Invited)(Plenary lecture)N. Yoshikawa, "Low-energy High-performance Computing based on Superconducting Technology", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 7, 3PL-01.
(24) Y. Yamanashi, R. Tsutumi, S. Shimizu, N. Yoshikawa, "High-Speed Operation of LR-Biased Single Flux Quantum Circuit with Dynamic Resetting of Mechanism of Bias Current", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 7 , 2016, 3EPo1B-01.
(25) Y. Yamanashi, R. Yamamoto, N. Yoshikawa, "Controllable Superconducting Phase Shifter Using Single Flux Quantum Circuit", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 7 , 2016, 3EPo1B-04.
(26) Q. Xu, C. L. Ayala,N. Takeuchi, Y. Murai, T. Ortlepp, Y. Yamanashi, No. Yoshikawa, "Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation with HDL Backend Verification", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 7 , 2016, 3EPo1C-05.
(27) (Invited)Y. Murai, C. L. Ayala, Y. Yamanashi and N. Yoshikawa, "Development and demonstration of a routing tool for large-scale adiabatic quantum-flux-parametron circuits with automatic buffer insertion", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 7 , 2016, 3EPo1C-06.
(28) N. Takeuchi, Y. Yamanashi, N. Yoshikawa, "Reversibility and energy dissipation in adiabatic quantum-flux-parametron logic", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 8 , 2016, 4EPo2A-02.
(29) K. Fang, T. Ando, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, "Study of multi-excitation AQFP circuits for high-speed and low-latency operations", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 8 , 2016, 4EPo2A-03.
(30) T. Ortlepp, T. Matsushima, Y. Yamanashi, N. Yoshikawa, "Performance comparison between a Josephson comparator and an adiabatic quantum flux parametron based comparator", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 8 , 2016, 4EPo2A-06.
(31) (Invited)G. Konno, Y. Yamanashi, N. Yoshikawa, "Fully Functional Operation of Low-Power 64-kb Josephson-CMOS Hybrid Memories", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 8 , 2016, 4EOr3A-01.
(32) A. Fujimaki, Y. Ito, M. Suzuki, M. Tanaka, G. Konno, N. Yoshikawa, "Josephson-CMOS Hybrid Memory with nanocryotrons", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 8 , 2016, 4EOr3A-02.
(33) T. Ono, Y. Yamanashi, N. Yoshikawa, "Design and implementation of an SFQ-based single-chip FFT processor", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr1B-03.
(34) K. Sano, T. Shimoda, Y. Abe, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, "Reduction of the supply current of single-flux-quantum time-to-digital converters by current recycling techniques for the operation in cryo-cooler", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr1B-07.
(35) (Invited)T. Narama, F. China, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Yield evaluation of 83k-junction adiabatic-quantum-flux-parametron circuit", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr2B-01.
(36) C. L. Ayala, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, "Majority-logic-optimized parallel prefix carry look-ahead adder families using adiabatic quantum-flux-parametron logic", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr2B-02.
(37) N. Tsuji, C. L. Ayala, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Design and implementation of 16-word by 1-bit register files using adiabatic quantum flux parametron logic", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr2B-03.
(38) F. China, N. Tsuji, T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Demonstration of Signal Transmission between Adiabatic Quantum-Flux-Parametrons and Rapid Single-Flux-Quantum Circuits Using Superconductive Microstrip Lines", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr2B-05.
(39) N. Takeuchi, H. Suzuki, Y. Yamanashi, N. Yoshikawa, "Design and demonstration of superconducting voltage drivers for adiabatic quantum-flux-parametron logic", 2016 Appl. Superconductivity Conference (ASC 2016), Denver, Colorado, USA, September 5 , 2016, 1EOr2B-06.
2017
(1) N. Yoshikawa, T. Igarashi, G. Konno, T. Takahashi, Y. Yamanashi, “Recent research development of memories for single-flux-quantum computing systems,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-3.
(2) N. Takeuchi, S. Nagasawa, F. China, T. Ando, M. Hidaka, Y. Yamanashi, N. Yoshikawa, “Adiabatic quantum-flux-parametron cell library developed using a 10 kA cm−2 niobium fabrication process,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-6.
(3) T. Igarashi, H. Suzuki, Y. Yamanashi, N. Yoshikawa, “Design and evaluation of loop drivers for SFQ memory cells and decoders,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-7.
(4) Q. Xu, Y. Murai, R.Saito, C. L. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “An EDA flow for AQFP VLSI design with customized interface to Cadence tools,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-8.
(5) H. Takayama, N. Tsuji, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Simulation of 4-bit random access memory cells composed of quantum flux parametron,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-9.
(6) Y. Yamanashi, Y. Ito, N. Takeuchi, N. Yoshikawa, “Investigation of reconfigurable superconducting reversible login gate,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-13.
(7) Y. Abe, K.Sano, N. Zen, G. Fujii, Y. Mawatari, Y. Yamanashi, N. Yoshikawa, “Study on the detection of single flux quantum in superconducting nano strip line,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-19.
(8) K.Sano, Y. Abe, Y. Yamanashi, N. Yoshikawa, “Measurement and evaluation of bias margins of driver/receiver circuits for current recycling technique,” 10th Superconducting SFQ VLSI Workshop (SSV2017), Nagoya, Japan, February 20-21, 2017, O-21.
(9) N. Tsuji, N. Takeuchi, C. Ayala, Y. Yamanashi, and N. Yoshikawa, “Design and implementation of scalable register files using adiabatic quantum flux parametron logic,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Fr-C-NJD-02.
(10) R. Sato, T. Ono, Y. Yamanashi, and N. Yoshikawa, “(Invited) Design and high speed demonstration of an SFQ complex event detector circuit for complex event processing,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Fr-I-DIG-03.
(11) Y. Xing, N. Takeuchi, K. Fang, Y. Yamanashi, and N. Yoshikawa, “Design and Demonstration of Power Divider for Adiabatic Quantum-Flux-Parametron Logic,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-01.
(12) Y. Yamanashi, A. Sugiyama, N. Yoshikawa, “Analog Circuit Simulator for Superconducting Circuits Containing pi-Josephson Junctions,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-13.
(13) C. L. Ayala, Q. Xu, Y. Murai, R. Saito, N. Takeuchi, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, “A Large-Scale Design Flow for Adiabatic Quantum-Flux-Parametron Circuits with Retiming and Fan-out Deconstruction,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-14.
(14) Q. Xu, R. Saito, Y. Murai, C. L. Ayala, N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Performance Analysis of Synthesized Benchmark Circuits Implemented in Adiabatic Superconductor Logic,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, Tu-SDM-15.
(15) Y. Yamanashi, H. Imai, N. Yoshikawa, “Influences of Magnetic Flux Trapped in Moats on Superconducting Integrated Circuit Operation,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-SDM-02.
(16) F. China, N. Tsuji, T. Ando, H. Takayama, N. Takeuchi, S. Nagasawa, M. Hidaka, Y. Yamanashi, and N. Yoshikawa, “High-density Integration of Adiabatic Quantum-Flux-Parametron Circuits by Using Double-Active-Layered Niobium Process,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-SDM-04.
(17) T. Matsushima, Y. Yamanashi, N. Takeuchi, N. Yoshikawa, and T. Ortlepp, “Analysis of Relationship between Gray Zone and Energy Dissipation of Adiabatic Quantum Flux Parametron,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-SDM-18.
(18) K. Sano, M. Suzuki, M. Tanaka, A. Fujimaki, N. Yoshikawa, “Fabricaton of NbTiN nanocryotrons for Josephson-CMOS hybrid memory application,” The 16th International Superconductive Electronics Conference (ISEC 2017), Sorrento, Italy, Jun. 12-16, 2017, We-C-HYB-04.
(19) N. Yoshikawa, “(Invited) Status of RSFQ developments in Japan,” International Workshop on Superconducting Quantum Technology, Freyburg/Unstrut, Germany, Jun. 18-21, 2017.
(20) N. Yoshikawa, “Adiabatic quantum flux parametron as an ultra-energy-efficient readout circuit for superconducting sensor arrays, ” International Workshop on Superconducting Quantum Technology, Freyburg/Unstrut, Germany, Jun. 18-21, 2017.
(21) N. Yoshikawa, “(Invited) Recent research developments of adiabatic quantum-flux-parametron circuits technology toward energy-efficient high-performance computing, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 4E01-01.
(22) Y. Abe, K. Sano, N. Zen, G. Fujii, Y. Mawatari, Y. Yamanashi, N. Yoshikawa, “Direct Detection of Single Flux Quantum Generated in Superconducting Strip Photon Detectors, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 4E01-05.
(23) T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Theory and experimental analysis of the sensitivity of an adiabatic quantum flux parametron, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 4E01-02.
(24) Q. Xu, C. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and implementation of AQFP-based register files for an AQFP 4-bit RISC microprocessor prototype, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 1EP1-12.
(25) C. Ayala, Q. Xu, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Microarchitectures for energy-efficient computing implemented in adiabatic quantum-flux-parametron logic, ” 13th European Conference on Applied Superconductivity (EUCAS 2017), Geneva, Switzerland, Sep. 17-21, 2017. 1EP1-06.
(26) N. Takeuchi, C. Ayala, Q. Xu, Y. Yamanashi, N. Yoshikawa, “(Invited) Current Progress in Adiabatic Quantum Flux Parametron, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. ED5-1-INV.
(27) Y. Tomitsuka, Y. Abe, Y. Yamanashi, N. Zen, M.Ohkubo, N. Yoshikawa, “Demonstration of picosecond time resolution of double-oscillator time-to-digital converters using single-flux-quantum circuits, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. ED5-4.
(28) H. Takayama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “A random-access-memory cell based on quantum flux parametron with three control lines, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-3.
(29) T. Matsushima, Y. Yamanashi, N. Takeuchi, N. Yoshikawa, “Proposal of superconducting analog to digital converter using quantum flux parametron, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-4.
(30) A. Sanada, Y. Yamanashi, N. Yoshikawa, “Study on Integer-Number Parallel Divider Based on Single Flux Quantum Logic, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-5.
(31) C. Ayala, Q. Xu, R. Saito, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design of an arithmetic logic unit and a data shifter for adiabatic quantum-flux-parametron-based microprocessor, ” The 30th International Symposium on Superconductivity (ISS2017), Tokyo, Japan, Dec. 14-15, 2017. EDP1-6.
2018
(1) "N. Takeuchi, C. Ayala, Q. Xu, H. Suzuki, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Recent Development and Applications of Adiabatic Quantum Flux Parametron Logic, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. O-6."
(2) "C. Ayala, N. Takeuchi, Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Adiabatic Quantum-Flux-Parametron-Based Microprocessor: Architecture, Logic Design, Modeling, and Design Tools, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. O-7."
(3) "F. Ke, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Design and Simulation of a 7-bit 18-sample/cycle SFQ-Based Sine Wave Generator, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. P-2."
(4) "K. Akizuki, R. Sato, Y. Yamanashi, N. Yoshikawa, “Design of an SFQ Complex Event Detector Circuit Corresponding to Regular Expressions, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. P-5."
(5) "M. Araki, Y. Yamanashi, N. Yoshikawa, “Design and Evaluation of a 4-Input Logic Block for Realization of FPGAs Using Single Flux Quantum Circuits, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. P-7."
(6) "T. Tamura, C. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Reduction of the Circuit Area of an 8-word by 1-bit Register Using Quantum Flux Parametron Latch, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. P-8."
(7) "T. Yamae, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and Simulation of Reversible Adders Using Adiabatic Quantum Flux Parametron Logic, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. P-9."
(8) "Y. Hironaka, C. Ayala, Y. Yamanashi, N. Yoshikawa, “Design of a 1-bit SFQ CPU and Comparison with CMOS and AQFP Circuits, ” The 11th Superconducting SFQ VLSI Workshop (SSV 2018) / 6th CRAVITY Symposium, Tsukuba, Japan, Feb. 7-8, 2018. P-10."
(9) "N. Yoshikawa, “AQFP circuit simulation, ” 1st South African Workshop on Superconducting Circuit Design Tools and Modelling 2018, Cape town, South Africa, Feb. 18-23, 2018."
(10) "N. Yoshikawa, “PTL + drivers/receivers, reflection, ” 1st South African Workshop on Superconducting Circuit Design Tools and Modelling 2018, Cape town, South Africa, Feb. 18-23, 2018."
(11) "N. Yoshikawa, “Simulation vs measurement at high frequency, ” 1st South African Workshop on Superconducting Circuit Design Tools and Modelling 2018, Cape town, South Africa, Feb. 18-23, 2018."
(12) "N. Yoshikawa, “(Invited) Recent Development of Extremely Energy-Efficient Integrated Circuits Using Adiabatic Flux Parametron,” The 14th International Workshop of High-Temperature Superconductors in High Frequency Field (HTSHFF2018), Zao, Yamagata, Japan, June 5-8, 2018."
(13) "C. Ayala, Q. Xu, R. Saito, T. Tanaka, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Execution units for a RISC-based adiabatic quantum-flux-parametron microprocessor datapath, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 1EOr1C-05."
(14) "A. Sanada, Y. Yamanashi, N. Yoshikawa, “Study on Single Flux Quantum Floating-Point Divider Based on Goldschmidt’s Algorithm, ” Applied Superconductivity Conference 2018 (ASC2018), Seattle, USA, Oct. 28- Nov. 2, 2018, 1EPo2E-05."
(15) "F. China, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “A High-Speed Voltage Driver using a 4JL Gate for Adiabatic Quantum Flux Parametron, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 1EPo2E-06."
(16) "Y. Tomitsuka, Y. Abe, N. Zen, Y. Yamanashi, N. Yoshikawa, “Demonstration of picosecond time resolution of double-oscillator time-to-digital converters using single-flux-quantum circuits, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 1EPo2E-07."
(17) "N. Takeuchi, T. Yamashita, S. Miyajima, S. Miki, N. Yoshikawa, H. Terai, “Demonstration of a superconducting nanowire single-photon detector using adiabatic quantum-flux-parametron logic in a 0.1 W Gifford–McMahon cryocooler, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 2EPo1B-06."
(18) "Y. Okuma, Y. Yamanashi, N. Yoshikawa, “Design and Implementation of a Low-Power Area-Efficient Adiabatic-Quantum-Flux-Parametron FPGA using Josephson-CMOS Hybrid Memories, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 2EOr1B-03."
(19) "Y. Yamanashi, S. Nakaishi, N. Yoshikawa, “[Invited] Evaluation of Single Flux Quantum Flip-Flops Containing π-Shifted Josephson Junctions, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 2EPo2E-02."
(20) "K. Arai, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Inverting quantum flux parametron as adiabatic superconductor logic without transformers, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 2EPo2E-09."
(21) "N. Takeuchi, C. Ayala, Q. Xu, N. Yoshikawa, “A feedback-friendly large-scale clocking scheme for adiabatic quantum-fluxparametronlogic datapaths, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 3EPo2D-08."
(22) "Y. He, N. Takeuchi, Q. Xu, N. Yoshikawa, “Superconducting microwave delay network for adiabatic quantum-flux-parametron logic, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 3EPo2D-09."
(23) "M. Nozoe, C. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and implementation of 16-word by 4-bit register file using adiabatic quantum flux parametron logic, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 3EOr2C-02."
(24) "Q. Xu, T. Tanaka, C. Ayala, N. Takeuchi, N. Yoshikawa, “Design of Adiabatic-Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 4EPo1D-04."
(25) "C. Fourie, M. Botha, P. Febvre, C. Ayala, Q. Xu, N. Yoshikawa, E. Patrick, M. Law, Y. Wang, M. Annavaram,P. Beerel, S. Gupta, S. Nazarian, M. Pedram, “[Invited] ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 4EOr2B-02"
(26) "T. Tanaka, C. Ayala, Q. Xu, R. Saito, N. Yoshikawa, “Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 4EOr2B-05."
(27) "T. Yamae, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and demonstration of reversible full adders using adiabatic quantum flux parametron logic, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 4EOr3C-01."
(28) "F. Ke, Y. Yamanashi, N. Yoshikawa, “Design and demonstration of an SFQ-based full-component singlechip FFT processor, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 4EOr3C-03."
(29) "Q. Xu, Y. Wang, X. Ma, N. Takeuchi, N. Yoshikawa, “Design and implementation of an extremely energy-efficient deep learning accelerator using superconducting logic, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 4EOr3C-04."
(30) "D. Scott Holmes, E. DeBenedictis, R. Fagaly, P. Febvre, D. Gupta, Anna. Herr, Anna Leese de Escobar, N. Missert, O. Mukhanov, Satyavolu Papa Rao, N. Yoshikawa, P. Gargini, “[Invited] Superconductor Electronics Technology Roadmap for IRDS 2018, ” Applied Superconductivity Conference (ASC2018), Seattle, USA, Oct. 28-Nov. 2, 2018, 5EOr1A-01."
(31) "N. Yoshikawa, “[Invited] High-speed and Low-power signal processing using superconducting circuits,” Workshop on the future of silicon detector technologies FuTuRe II, Erfurt, Germany, December 2-4, 2018."
(32) "C. Ayala, Olivia Chen, R. Saito, T. Tanaka, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “[Invited] Development of an extremely energy-efficient AQFP microprocessor, ” The 31st International Symposium on Superconductivity (ISS2018), Ibaraki, Japan, Dec. 12-14, 2018, ED5-2-INV."
(33) "T. Tamura, N. Takeuchi, C. Ayala, Y. Yamanashi, N. Yoshikawa, “Area Reduction of Adiabatic-Quantum-Flux-Parametron Register-Files by Using Asymmetric Gates, ” The 31st International Symposium on Superconductivity (ISS2018), Ibaraki, Japan, Dec. 12-14, 2018, EDP-2-1."
(34) "Y. Hironaka, Y. Yamanashi, N. Yoshikawa, “Design and evaluation of a one-instruction-set single-flux-quantum microprocessor for the demonstration of Josephson-CMOS hybrid system, ” The 31st International Symposium on Superconductivity (ISS2018), Ibaraki, Japan, Dec. 12-14, 2018, EDP-2-2."
(35) "F. Ke, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Design and demonstration of an 8-bit 18-sample/cycle sine code generator using single-flux-quantum circuits, ” The 31st International Symposium on Superconductivity (ISS2018), Ibaraki, Japan, Dec. 12-14, 2018, EDP-2-3."
(36) "M. Araki, Y. Yamanashi, N. Yoshikawa, “Design and measurement of 4-unit 2-bit FPGA using single-flux-quantum circuits, ” The 31st International Symposium on Superconductivity (ISS2018), Ibaraki, Japan, Dec. 12-14, 2018, EDP-2-4."
(37) "M. Nozoe, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Demonstration of 5.6 ps Latency of Adiabatic Quantum Flux Parametron using Delayed Clocking Scheme, ” The 31st International Symposium on Superconductivity (ISS2018), Ibaraki, Japan, Dec. 12-14, 2018, EDP-2-4."
2019
(1) "N. Yoshikawa, Y. Yamanashi, N. Takeuchi, C. Ayala, A. Fujimaki, M. Tanaka, M. Hidaka “Study on Adiabatic Single-Flux-Quantum Circuits Approaching the Thermodynamic Energy Limit,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, O-2."
(2) "Y. Hironaka, Y. Yamanashi, N. Yoshikawa, “Design of a One-Instruction-Set SFQ Microprocessor for High-Speed Demonstration of SFQ/CMOS Hybrid System,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-3."
(3) "F. Ke, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “56-GHz demonstration of a 13-bit 50-sample/period SFQ-based sine code generator using 10 kA/cm2 Nb process,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-4."
(4) "O. Chen, F. Ke, R. Saito, R. Cai, Y. Wang, N. Yoshikawa, “AQFP-SYNTH: A Performance Evaluation Framework for Adiabatic Quantum-Flux-Parametron Based Circuits and Systems,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-8."
(5) "T. Tamura, C. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and Measurement of a 5-to-31 Decoder Using Offset Adiabatic Quantum Flux Parametron Gates,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-9."
(6) "T. Tanaka, C. Ayala, Q. Xu, R. Saito, N. Yoshikawa, “Measurement Result of Adiabatic Quantum Flux Parametron 4-bit Shifter-Rotator Circuit Designed by Automatic Placement,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-10."
(7) "T. Yamae, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and Measurement of a Reversible 4-to-16 Decoder Using Adiabatic Quantum-Flux-Parametron Logic,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-11."
(8) "Y. Yamazaki, Y. Yamanashi, N. Yoshikawa, “Design and Simulation of a Five-Input Majority Gate Using Adiabatic Quantum Flux Parametron Logic,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-12."
(9) "S. Michibayashi, N. Takeuchi, Y. Yamanashi, N. Yoshikawa,“A Proposal of a Microwave Chopper Using Single-Flux-Quantum Circuits with Controllable Amplitude of Microwave,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-15."
(10) "Y. He, N. Takeuchi, N. Yoshikawa, “Compact High Selectivity In-Line Topology Filter Based on LTS Technology, ” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, Jan. 16-17, 2019, P-20."
(11) "Y. Tsuna, Y. Yamanashi, N. Yoshikawa, “Simulation of Superconductor Circuit Operation Considering 1/f Noises,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-21."
(12) "D. Yamaguchi, Y. Yamanashi, N. Yoshikawa, “Investigation of Superconducting Neural Network Realizing Arbitrary Logic Function,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-22."
(13) "K. Akizuki, Y. Yamanashi, N. Yoshikawa, “Measurement of an SFQ 1-Symbol Matching Circuit Corresponding to Regular Expressions,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, P-24."
(14) "C. L. Ayala, N. Yoshikawa, “New Directions for Adiabatic Quantum-Flux-Parametron Logic Computing,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, O-4."
(15) "N. Takeuchi, T. Yamashita, S. Miyajima, S. Miki, N. Yoshikawa, H. Terai, “Adiabatic Quantum-Flux-Parametron Logic as a Readout Interface for Superconducting Nanowire Single Photon Detectors,” 12th Superconducting SFQ VLSI Workshop (SSV 2019), Kobe, Japan, January 16-17, 2019, O-9."
(16) "N. Yoshikawa, “Thin-film basics and device manufacture,” South African Superconducting Quantum electronic circuit design tools and Analysis workshop (SASQIA 2019), Hermanus, Cape Town, March 3-8, 2019, D1L3."
(17) "N. Yoshikawa, “AQFP circuit design and simulation,” South African Superconducting Quantum electronic circuit design tools and Analysis workshop (SASQIA 2019), Hermanus, Cape Town, March 3-8, 2019, D2L5."
(18) "N. Yoshikawa, “Passive transmission lines matching and layout,” South African Superconducting Quantum electronic circuit design tools and Analysis workshop (SASQIA 2019), Cape Town, South Africa, March 3-8, 2019, D5L3."
(19) "R. Saito, C. L. Ayala, O. Chen, T. Tanaka, N. Yoshikawa, “Automatic Top-Down Methodology with Retiming Optimization for Adiabatic Quantum-Flux-Parametron Logic,” South African Superconducting Quantum electronic circuit design tools and Analysis workshop (SASQIA 2019), Cape Town, South Africa, March 3-8, 2019."
(20) "T. Tanaka, C. L. Ayala, O. Chen, R. Saito, N. Yoshikawa, “Measurement Result of Adiabatic Quantum-Flux-Parametron 4-bit Shifter-Rotator Circuit Designed by Automatic Placement,” South African Superconducting Quantum electronic circuit design tools and Analysis workshop (SASQIA 2019), Cape Town, South Africa, March 3-8, 2019."
(21) "K. Fei, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Demonstration and evaluation of a 13-bit 50-sample/period SFQ-based sine code generator,” South African Superconducting Quantum electronic circuit design tools and Analysis workshop (SASQIA 2019), Cape Town, South Africa, March 3-8, 2019."
(22) "N. Yoshikawa, “(Tutorial) Library design and design tools for adiabatic quantum-flux-parametron logic circuits (ac-biased SFQ logic),” Design, Automation and Test in Europe (DATE 2019), Florence, Italy, March 25-29, 2019."
(23) "R. Cai, O. Chen, A. Ren, N. Liu, C Ding, N. Yoshikawa, Y. Wang, “A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits,” Great Lakes Symposium on VLSI (GLSVLSI 2019), pp. 189-194, Tysons Corner, VA, USA, May 09-11, 2019."
(24) "N. Yoshikawa, “(Keynote) Asynchronous Superconducting Digital Circuits,” 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan, May 12-15, 2019."
(25) "R. Cai, A. Ren, O. Chen, N. Liu, C. Ding, X. Qian, J.Han, W. Luo, N. Yoshikawa, Y. Wang, “A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology,” Proceedings of the 46th International Symposium on Computer Architecture (ISCA2019), Phoenix, Arizona, June 22-26, 2019, pp. 567-578"
(26) "N. Yoshikawa, “(Keynote) Superconducting computing: present status and perspectives,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(27) "T. Tamura, N. Takeuchi, C. L. Ayala, Y. Yamanshi, N. Yoshikawa, “Design and Implementation of Compact Register Files Using Adiabatic Quantum Flux Parametron Logic,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(28) "Y. Tsuna, Y. Yamanshi, N. Yoshikawa, “Investigation of the effects of 1/f noise on superconducting circuits,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(29) "C. L. Ayala, O. Chen, N. Yoshikawa, “AQFPTX: Adiabatic Quantum-Flux-Parametron Timing eXtraction Tool,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(30) "N. Takeuchi, F. China, S. Miki, S. Miyajima, M. Yaburo, N. Yoshikawa, H. Terai, “Scalable readout circuits for superconducting nanowire single-photon detectors using adiabatic quantum-flux-parametron and rapid single-flux-quantum logic families,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(31) "Y. He, N. Takeuchi, N. Yoshikawa, “High Selectivity In-Line Topology LTS Filter Based on Direct Synthesis Method,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(32) "K. Akizuki, Y. Yamanshi, N. Yoshikawa, “Measurement of an SFQ complex event detector for complex event processing,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(33) "N. Takeuchi, M. Nozoe, Y. He, N. Yoshikawa, “Low-latency adiabatic quantum-flux-parametron using delay-line clocking,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(34) "T. Tanaka, C. L. Ayala, O. Chen, R. Saito, N. Yoshikawa, “Quality of Results of Adiabatic Quantum-Flux-Parametron Integrated Circuits Placed by the Genetic Algorithm,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(35) "T. Yamae, N. Takeuchi, C. L. Ayala, H. Suzuki, N. Yoshikawa, “Demonstration and energy evaluation of an 8-bit carry look-ahead adder using adiabatic quantum-flux-parametron logic,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(36) "Y. Hironaka, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Demonstration of a single-flux-quantum microprocessor operating with a Josephson-CMOS hybrid memory,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(37) "C. L. Ayala, T. Tanaka, M. Nozoe, N. Takeuchi, N. Yoshikawa, “Component Demonstration of a RISC-based AQFP MANA Processor,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28- August 1, 2019."
(38) "H. Terai, M. Yaburo, S. Miyajima, S. Miki, F. China, N. Takeuchi, N. Yoshikawa, H. Terai, “Single-photon camera with a superconducting nanowire single-photon detector array and cryogenic digital signal processing,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(39) "Y. Yamanashi, A. Sanada, N. Yoshikawa, “Measurement of Single-Flux-Quantum Floating-Point Divider Based on Goldschmidt's Algorithm,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28- August 1, 2019."
(40) "T. Yamae, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “A flip-flop and a decoder for reversible quantum-flux-parametron register files,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(41) "T. Tanaka, R. Cai, Y. Wang, N. Yoshikawa, “Design and implementation of a bitonic sorter based DCNN using adiabatic superconducting logic,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(42) "C. Fourie, L. Schindler, C. L. Ayala, T. Tanaka, R. Saito, N. Yoshikawa, “Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families,” The 17th International Superconductive Electronics Conference (ISEC 2019), Riverside, California, USA, July 28-August 1, 2019."
(43) "N. Yoshikawa, “(Invited) Recent progress of adiabatic-quantum-flux-parametron circuit technologies,” The 14th European Conference on Applied Superconductivity (EUCAS 2019), Glasgow, Scotland, September 1–5, 2019."
(44) "F. Ke, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “High-Speed Operation of a 13-bit 50-sample/period SFQ-based Sine Code Generator,” The 14th European Conference on Applied Superconductivity (EUCAS 2019), Glasgow, Scotland, September 1–5, 2019."
(45) "Y. He, N. Takeuchi, N. Yoshikawa, “Low-latency AQFP logic by using serial-type power dividers,” The 14th European Conference on Applied Superconductivity (EUCAS 2019), Glasgow, Scotland, September 1–5, 2019."
(46) "Y. He, C. L. Ayala, N. Takeuchi, T. Yamae, Y. Hironaka, N. Yoshikawa, “A Compact AQFP Logic Cell Design Using an 8-Metal Layer Superconductor Process,” The 14th European Conference on Applied Superconductivity (EUCAS 2019), Glasgow, Scotland, September 1–5, 2019."
(47) "O. Chen, W. Luo, R. Cai, N. Takeuchi, Y. Wang, N. Yoshikawa, “A novel stochastic number generator using adiabatic superconducting technology,” The 14th European Conference on Applied Superconductivity (EUCAS 2019), Glasgow, Scotland, September 1–5, 2019."
(48) "N. Yoshikawa, N. Takeuchi, C. Ayala, O. Chen, Y. He, Y. Yamanashi, “Extremely Energy-Efficient Circuit Technology based on Adiabatic Quantum Flux Parametron,” The 10th East Asia Symposium on Superconductor Electronics (EASSE-2019), Beijing, China, October 8-11, 2019."
(49) "H. Terai, M. Yabuno, S. Miyajima, S. Miki, F. China, N. Takeuchi, N. Yoshikawa, “Recent progress in research and development of superconducting nanowire single-photon detectors,” The 10th East Asia Symposium on Superconductor Electronics (EASSE-2019), Beijing, China, October 8-11, 2019."
(50) "F. Ke, Y. Yamanashi, N. Yoshikawa, “Design and High-speed Test of an SFQ-based Single-chip FFT Processor,” The 32st International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, ED4-6."
(51) "R. Saito, C. L. Ayala, O. Chen, T. Tanaka, N. Yoshikawa, “Development of Majority-Logic-Based Top-Down Environment for Adiabatic Quantum-Flux-Parametron Circuits,” The 32st International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-5."
(52) "N. Yoshikawa, “Energy-Efficient Superconducting Digital Circuit Technology for High Performance Computation,” Joint KU-VUW Workshop 2019, Portage, New Zealand, November 10-12, 2019."
(53) "N. Yoshikawa, “High-Speed and High-Sensitivity Sensor Readout and Signal Processing using Superconducting Circuits,” Workshop on the Future of Silicon Detector Technologies (FuTuRe), Erfurt, Germany, December 2-3, 2019."
(54) "F. Ke, Y. Yamanashi, N. Yoshikawa, “Design and High-speed Test of an SFQ-based Single-chip FFT Processor,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, ED4-6."
(55) "Z. Li, Y. Yamanashi, N. Yoshikawa, “Single-Flux-Quantum Parallel Multiplier Using Accumulator Unit,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-2."
(56) "T. Tanaka, C. L. Ayala, N. Yoshikawa, “Investigation of influence by flux trapping for interconnection of adiabatic quantum-flux-parametron circuits,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-3."
(57) "Y. Tsuna, Y. Yamanashi, N. Yoshikawa, “Numerical and Experimental Analysis of Influences of 1/f noises on Superconducting Integrated Circuits,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-4."
(58) "R. Saito, C. L. Ayala, O. Chen, T. Tanaka, N. Yoshikawa, “Development of Majority-Logic-Based Top-Down Environment for Adiabatic Quantum-Flux-Parametron Circuits,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-5."
(59) "L. Shirakawa, Y. Yamanashi, N. Yoshikawa, “Design and evaluation of multi-bit-input single-flux-quantum autocorrelator system for astronomical data analysis,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-6."
(60) "C. L. Ayala, N. Takeuchi, N. Yoshikawa, “Adiabatic Quantum-Flux-Parametron Design-For-Testability Components for Large-Scale Digital Circuits,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-7."
(61) "T. Yamae, N. Takeuchi, N. Yoshikawa, “Investigation on the Method to Evaluate the Energy Dissipation of General Adiabatic Quantum-Flux-Parametron Logic Gates,” The 32nd International Symposium on Superconductivity (ISS2019), Kyoto, Japan, December 3-5, 2019, EDP2-8."