1993

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1994

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1995

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(1)　N. Yoshikawa, H. Ishibashi and M. Sugahara, "Dynamic Characteristics of Inverter Circuits Using Single Electron Transistor", Jpn. J. Appl. Phys. 34, pp.1332-1338 (1995).

(2)　N. Yoshikawa, N. Miura, X. Chen, K. Yokoyama and M. Sugahara, "Electrical Field Effect in Highly Resistive NbN Microbridge", IEEE Trans. on Applied Superconductivity, 5, pp.3090-3093 (1995).

(3)　H. Fukuzawa, H. Kimijima, N. Yoshikawa and M. Sugahara, "Fabrication of Pd Nanostructures with Scanning Tunneling Microscope", Jpn. J. Appl. Phys. 34, pp.L1221-L1223 (1995).

(4)　N. Miura, N. Yoshikawa and M. Sugahara, "Coulomb blockade and electrical field effect in nanoscale granular microbridges", Appl. Phys. Lett. 67, pp.3969-3971 (1995).
 

​

1996

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(1)　H. Su, N. Yoshikawa and M. Sugahara, "Study of electrical conduction properties of NbN thin films using NbN/MgO/NbN double tunnel junctions", Supercond. Sci. Technol. 9, pp.A152-A155 (1996).

(2)　N. Yoshikawa, Y. Jinguu, H. Ishibashi and M. Sugahara, "Complementary Digital Logic Using Resistively Coupled Single Electron Transistor", Jpn. J. Appl. Phys. 35, pp.1140-1145 (1996).

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1997

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(1)　Z. J. Deng, N. Yoshikawa, S. R. Whiteley and T. Van Duzer, "Data-Driven Self-Timed RSFQ Digital Integrated Circuit and System", IEEE Trans. on Applied Superconductivity, Vol. 7, June, 1997, pp.3634-3637.

(2)　N. Yoshikawa, H. Kimijima, N. Miura and M. Sugahara, "Single-Electron-Tunneling Effect in Nanoscale Granular Microbridge", Jpn. J. Appl. Phys. 36, pp. 4161-4165 (1997).

(3)　Z. J. Deng, N. Yoshikawa, S. R. Whiteley and T. Van Duzer, "Data-Driven Self-Timed RSFQ High Speed Test System", IEEE Trans. Appl. Superconductivity, Vol. 7, December,1997, pp. 3830 - 3833.

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1998

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(1)　N. Yoshikawa, H. Tago and K. Yoneyama, "Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits", IEICE Transactions on Electronics vol. E81-C, No. 10 October 1998, pp. 1618 - 1626.

(2)　N. Yoshikawa, H. Tago and K. Yoneyama, "A New Design Approach for RSFQ Logic Circuits Based on the Binary Decision Diagram", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.3161-3164.

(3)　Z. J. Deng, H. Zhang, N. Yoshikawa, U. Ghoshal, E. Fang, A. Flores, L. Zheng, S. R. Whiteley and T. Van Duzer, "Memory-Processor Interface with Hybrid CMOS-RSFQ Technology", Applied Superconductivity, vol. 6, pp. 355-360, 1998.

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1999

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(1)　N. Yoshikawa, C. Fukuzato and M. Sugahara, "Single Electron Transfer Logic Gate Family", Jpn. J. Appl. Phys. 38 (1999) pp. 433-438.

(2)　N. Yoshikawa, H. Tago and K. Yoneyama, "A New Design Approach for RSFQ Logic Circuits Based on the Binary Decision Diagram", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.3161-3164.

(3)　N. Yoshikawa, Z. J. Deng, S. R. Whiteley and T. Van Duzer, "Simulation and 18 Gb/s Testing of a Data-Driven Self-Timed RSFQ Demultiplexer", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.4349-4352.

(4)　L. Zheng, N. Yoshikawa, Z. J. Deng, X. Meng, S. R. Whiteley and T. Van Duzer, "20 GHz RSFQ Multiplexer and Demultiplexer", IEEE Trans. Appl. Superconductivity, vol. 9, June, 1999, pp.3310-3313.

(5)　Z. J. Deng, N. Yoshikawa, S. R. Whiteley and T. Van Duzer, "Self-Timing and Vector Processing in RSFQ Digital Circuit Technology", IEEE Trans. Appl. Superconductivity, vol. 9, March, 1999, pp.7-17.

(6)　N. Yoshikawa and J. Koshiyama, "A Cell-Based Design Approach for RSFQ Circuits using Binary Decision Diagram", Superconductor Science and Technology, vol. 12, 1999, pp.918-920.

(7)　N. Yoshikawa and Y. Kato, "Reduction of Power Consumption of RSFQ Circuits by Inductance-Load-Biasing", Superconductor Science and Technology, vol. 12, 1999, pp.782-785.

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​

2000

​

(1)　N. Yoshikawa and K. Yoneyama, "Parameter Optimization of Single Flux Quantum Digital Circuits Based on Monte Carlo Yield Analysis", IEICE Transactions on Electronics vol. E83-C, No. 1 January, 2000, pp. 75 - 80.

(2)　越山潤一、吉川信行, "RSFQ論理回路のセルベース設計手法の検討", 電子情報通信学会論文誌C vol. J83-C, No. 7 pp. 636-642 2000年7月.

(3)　吉川信行、森静香、越山潤一, "Verilog HDLによるRSFQ論理回路のタイミング設計手法の検討", 電子情報通信学会論文誌C vol. J83-C, No. 7 pp. 643-650 2000年7月.
 

​

2001

​

(1)　N. Yoshikawa and J. Koshiyama, "Top-Down RSFQ Logic Design Based on a Binary Decision Diagram", IEEE Trans. Appl. Superconductivity, vol. 11, March, 2001, 1098-1101.

(2)　J. Koshiyama and N. Yoshikawa, "A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram", IEEE Trans. Appl. Superconductivity, vol. 11, March, 2001, pp. 263-266.

(3)　N. Yoshikawa, T. Abe, Y. Kato and H. Hoshina, "Component Development for a 16 Gb/s RSFQ-CMOS Interface System", IEEE Trans. Appl. Superconductivity, vol. 11, March, 2001, pp. 735-738.

(4)　N. Yoshikawa, J. Koshiyama, K. Motoori, F. Matsuzaki and K. Yoda, "Cell-based top-down design methodology for RSFQ digital circuits", Physica C 357-360, 2001, pp. 1529-1539.

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​

2002

​

(1)　A. Fujimaki, Y. Takai and N. Yoshikawa, "High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology", IEICE Transactions on Electronics, vol. E85-C, No. 3, 2002, pp. 612-616.

(2)　F. Matsuzaki, K. Yoda, J. Koshiyama, K. Motoori and N. Yoshikawa, "Design of small RSFQ Microprocessor based on Cell-Based Top-Down Design Methodology", IEICE Transactions on Electronics, vol. E85-C, No. 3, 2002, pp. 659-664.

(3)　N. Yoshikawa, K. Yoda, H. Hoshina and F. Matsuzaki, "Cell-Based Design Methodology for BDD RSFQ Logic Circuits　-Tolerance of Basic Cells to Circuit Parameter Variations", Supercond. Sci. Technol., vol. 15, 2002, pp. 156-160.

(4)　T. Van Duzer, L. Zheng, X. Meng, C. Loyo, S.R. Whiteley, L. Yu, N. Newman, J.M. Rowell, N. Yoshikawa, "Engineering issues in high-frequency RSFQ circuits", Physica C 372-376, 2002, pp. 1-6.

(5)　N. Yoshikawa, F. Matsuzaki, N. Nakajima and K. Yoda, "Design and Component Test of a 1-bit RSFQ Microprocessor", Physica C 378-381, 2002, pp. 1454-1460.

(6)　K. Fujiwara, H. Hoshina, J. Koshiyama, and N. Yoshikawa, "Design and Component Test of RSFQ Packet Decoders for Shift Register Memories", Physica C378-381, 2002, pp. 1475-1480.

(7)　吉川信行, "SFQ/半導体ハイブリッドメモリー", 応用物理, 第71巻, 第１号, 2002, pp. 76-77.

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​

2003

​

(1)　N. Yoshikawa, F. Matsuzaki, N. Nakajima, K. Fujiwara, K. Yoda and K. Kawasaki, "Design and Component Test of a Tiny Processor based on the SFQ Technology", IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.441-445.

(2)　N. Yoshikawa, K. Yoda, H. Hoshina, K. Kawasaki, K. Fujiwara, F. Matsuzaki, and N. Nakajima, "Cell Based Design Methodology for BDD SFQ Logic Circuits: a High Speed Test and Feasibility for Large Scale Circuit Applications," IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.523-526.

(3)　K. Fujiwara, H. Hoshina, Y. Yamashiro, N. Yoshikawa, "Design and Component Test of SFQ Shift Register Memories", IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.555-558.

(4)　Y.J. Feng, X. Meng, S. R. Whiteley, T. Van Duzer, K. Fujiwara, H. Miyakawa, N. Yoshikawa, "Josephson-CMOS hybrid memory with ultra-high-speed interface circuit", IEEE Trans. Appl. Superconductivity. vol. 13, June, 2003, pp.467-470.

(5)　F. Matsuzaki, N. Yoshikawa, M. Tanaka, A. Fujimaki, Y. Takai, "A Behavioral-Level HDL Description of SFQ Logic Circuits for Quantitative Performance Analysis of Large-Scale SFQ Digital Systems", Physica C 392-396, 2003, pp.1467-1471.

(6)　K. Fujiwara, H. Miyakawa, N. Yoshikawa, Y. Feng, S.R. Whiteley, T. Van Duzer, "Implementation and Low Speed Test of Ultra-Fast Interface Circuits for Josephson-CMOS Hybrid Memories", Physica C 392-396, 2003, pp. 1495-1500.

(7)　M. Tanaka, T. Kondo, A. Sekiya, A. Fujimaki, H. Hayakawa, F. Matsuzaki, N. Yoshikawa, H. Terai, S. Yorozu, "Component test toward single-flux-quantum processors", Physica C 392-396, 2003, pp. 1490-1494.

(8)　H. Terai, Y. Kameda, S. Yorozu, A. Kawakami, N. Yoshikawa and Z. Wang, "High-speed testing of tandem-Banyan network switch component", Physica C 392-396, 2003, pp. 1485-1489.

(9)　S. Yorozu, Y. Kameda, Y. Hashimoto, H. Terai, A. Fujimaki and N. Yoshikawa, "Single flux quantum circuit technology innovation for backbone router applications", Physica C 392-396, 2003, pp.1478-1484.

(10)　N. Harada, N. Yoshikawa, K. Yoda, A. Yoshida and N. Yokoyama, "Logic Operation at 5 Gbps of an Output Interface for Single Flux Quantum Systems", IEEE Trans. Applied Superconductivity, vol. 13, September, 2003, pp.3814-3817.

(11)　K. Kawasaki, K. Yoda, N. Yoshikawa, A. Fujimaki, H. Terai and S. Yorozu, "Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram," Supercond. Sci. Technol. 16 (2003) pp. 1497-1502.

(12)　K. Fujiwara, Y. Yamashiro, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu, "Design and high-speed test of 4 x 8-bit SFQ shift register files," Supercond. Sci. Technol. 16 (2003) pp. 1456-1459.

(13)　T. Hanai, T. Matsumoto, S. Yorozu, Y. Kameda, H. Terai, N. Yoshikawa, A. Fujimaki and H. Hayakawa, "Design of the speedup buffer for the single-flux-quantum network switch," Supercond. Sci. Technol. 16 (2003) pp. 1452-1455.

(14)　M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, H. Terai, S. Yorozu, N. Yoshikawa, A. Fujimaki and H. Hayakawa, "Prototypic design of the single-flux-quantum microprocessor, CORE1," Supercond. Sci. Technol. 16 (2003) pp. 1460-1463.

(15)　H. Terai, S. Yorozu, A. Fujimaki, N. Yoshikawa and Z. Wang, "A new design approach based on a multi-wiring-layer process for high-density SFQ circuits," Supercond. Sci. Technol. 16 (2003) pp. 1464-1469.

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​

2004

​

(1)　N. Nakajima, F. Matsuzaki, Y. Yamanashi, N. Yoshikawa, M. Tanaka, T. Kondo, A. Fujimaki, H. Terai and S. Yorozu, "Design and implementation of circuit components of the SFQ microprocessor, CORE1," Supercond. Sci. Technol. 17 (2004) pp. 301 - 307.

(2)　Y. Yamanashi, M. Ito, A. Tagami, and N. Yoshikawa, "High-speed measurement method of quantized energy levels in Josephson junctions using SFQ circuits," Physica C, vol. 412-414, 2004, pp. 1546-1549.

(3)　M. Ito, N. Nakajima, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu, "Design and implementation of SFQ programmable clock generators," Physica C, vol. 412-414, 2004. pp. 1550-1554.

(4)　H. Hayakawa, N. Yoshikawa, S. Yorozu and A. Fujimaki, "Superconducting Digital Electronics", Proceedings of the IEEE. vol. 92, October 2004, pp. 1549-1563.

(5)　N. Harada, N. Yoshikawa, A. Yoshida, and N. Yokoyama, "Josephson Latching Driver with a Low Bit-Error Rate", IEEE Trans. Applied Superconductivity. vol. 14, 2004, pp. 2031-2036.

(6)　H. Terai, Z. Wang, Y. Hishimoto, S. Yorozu, A. Fujimaki and N. Yoshikawa. "Timing jitter measurement of single-flux-quantum pulse in Josephson transmission line", Appl. Phys. Lett. 84, pp.2133-2135 (2004).

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​

2005

​

(1)　Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, and N. Yoshikawa, "Development of Passive Interconnection Technology for SFQ Circuits", IEICE TRANS. ELECTRON. vol. E88-C, 2005 pp. 198-207.

(2)　Y. Kameda S.Yorozu, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa, "High-Speed Demonstration of Single-Flux-Quantum Cross-Bar Switch up to 50 GHz", IEEE Trans. Applied Superconductivity. vol. 15, 2005 pp.6-10.

(3)　H. Kojima, Y. Yamashiro, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai and S. Yorozu "Parameter optimization of a Josephson latching driver based on bit-error-rate simulations", Physica C, vol. 426-431, Part 2, 1 October 2005, pp. 1680-1686.

(4)　A. Akimoto, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, S. Yorozu and H. Terai, "Consideration of logic synthesis and clock distribution networks for SFQ logic circuits", Physica C, vol. 426-431, Part 2, 1 October 2005, pp.1687-1692.

(5)　M. Tanaka, T. Kondo, T. Kawamoto, Y. Kamiya, K. Fujiwara, Y. Yamanashi, A. Akimoto, A. Fujimaki, N. Yoshikawa, H. Terai and S. Yorozu, "Design of a datapath for single-flux-quantum microprocessors with multiple ALUs", Physica C, vol.426-431, Part 2, 1 October 2005,pp .1693-1698.

(6)　T. Nishigai, M. Ito, N. Yoshikawa, A. Fujimaki, H. Terai and S. Yorozu, "Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits", Physica C, vol. 426-431, Part 2, 1 October 2005, pp. 1699-1703.

(7)　M. Ito, K. Kawasaki, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "20 GHz operation of bit-serial handshaking systems using asynchronous SFQ logic circuits", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp.255-258.

(8)　N. Yoshikawa, T. Tomida, M. Tokuda, Q. Liu, X. Meng, S. R. Whiteley, T. Van Duzer, "Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp.267-271.

(9)　T. Yamada, M. Yoshida, T. Hanai, A. Fujimaki, H. Hayakawa, Y. Kameda, S. Yorozu, H. Terai, N. Yoshikawa, "Quantitative evaluation of the single-flux-quantum cross/bar switch", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 324-327.

(10)　Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, N. Yoshikawa, "Implementation of a 4 x 4 switch with passive interconnects", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 356-359.

(11)　Y. Kameda, S. Yorozu, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa, "Single-flux-quantum (SFQ) circuit design and test of crossbar switch scheduler", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 423-426.

(12)　H. Terai, Y. Hashimoto, S. Yorozu, A. Fujimaki, N. Yoshikawa, Z. Wang, "The relationship between bit-error rate, operating speed and circuit scale of SFQ circuits", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 364-367.

(13)　K. Fujiwara, N. Nakajima, T. Nishigai, M. Ito, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, "Error rate test of large-scale SFQ digital circuit systems", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 427-430.

(14)　T. Nishigai, M. Ito, N. Yoshikawa, K. Obata, K. Takagai, N. Takagai, A. Fujimaki, H. Terai, S.Yorozu, "Advanced design approaches for SFQ logic circuits based on the binary decision diagra ", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 380-383.

(15)　M. Tanaka, T. Kondo, N. Nakajima, T. Kawamoto, Y. Yamanasi, Y. Kamiya, A. Akimoto, A. Fujimaki, H. Hayakawa, N. Yoshikawa, H. Terai, Y. Hashimoto, S. Yorozu, "Demonstration of a single-flux-quantum microprocessor using passive transmission lines", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 400-404.

(16)　S. Yorozu, Y. Kameda, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa, "Progress of single flux quantum packet switch technology", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 411-414.

(17)　Q. Liu, T. Van Duzer, X. Meng, S.R. Whiteley, K. Fujiwara, T. Tomida, K. Tokuda, N. Yoshikawa, "Simulation and measurements on a 64-kbit hybrid Josephson-CMOS memory", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 415-418.

(18)　Y. Yamanashi, M. Ito, A. Tagami, N. Yoshikawa, "Observation of quantized energy levels in a Josephson junction using SFQ circuits", IEEE Trans. Applied Superconductivity. vol. 15, June 2005, pp. 864-867.

(19)　Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, N. Yoshikawa, "Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits", IEEE Trans. Applied Superconductivity. vol. 15, September 2005, pp. 3814-3820.

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​

2006

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(1)　K. Fujiwara, T. Hikida, N. Yoshikawa, A. Fujimaki, S. Yorozu, H. Terai, “The influence of the ground current on large-scale single-flux-quantum circuits,” Supercond. Sci. Technol. 19 (2006) S362-S365.

(2)　Y. Yamanashi, A. Akimoto, N. Yoshikawa, M. Tanaka, T. Kawamoto, Y. Kamiya, A. Fujimaki, H. Terai and S. Yorozu, “A new design approach for control circuits of pipelined single-flux-quantum microprocessors,” Supercond. Sci. Technol. 19 (2006) S340-S343.

(3)　N. Yoshikawa, M. Tokuda1, T. Tomida, H. Kojima, K. Fujiwara, Q. Liu and T. Van Duzer, “Access time measurements of Josephson-CMOS hybrid memory using single-flux-quantum circuits,” Supercond. Sci. Technol. 19 (2006) S350-S353.

(4)　T. Nishigai, S. Yamada, N. Yoshikawa, “Design and implementation of low-power SFQ circuits using LR-load biasing technique,” Physica C, vol. 445-448, October 2006, pp. 1029-1033.

(5)　H. Terai, S. Yorozu, A. Fujimaki, N. Yoshikawa, Z. Wang, “Signal integrity in large-scale single-flux-quantum circuit,” Physica C, vol. 445-448, October 2006, pp. 1003-1007

(6)　Y. Yamanashi, T. Asano, N. Yoshikawa, “On-chip microwave generator for manipulation of superconductive quantum bits,” Physica C, vol. 445-448, October 2006, pp. 967-970.

(7)　Y. Kameda, S. Yorozu, Y. Hashimoto, H. Terai, A. Fujimaki, N. Yoshikawa, “40-GHz operation of a single-flux-quantum (SFQ) 4 x 4 switch scheduler,” Physica C, vol. 445-448, October 2006, pp. 1008-1013.

(8)　K. Obata, M. Tanaka, Y. Tashiro, Y. Kamiya, N. Irie, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, “Single-flux-quantum integer multiplier with systolic array structure,” Physica C, vol. 445-448, October 2006, pp. 1014-1019.

(9)　Y. Hashimoto, S. Yorozu, Y. Kameda, H. Suzuki, T. Miyazaki, H. Kojima, N. Yoshikawa, “Implementation and experimental evaluation of a cryocooled system prototype for high-throughput SFQ digital applications” Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EX01

(10)　M. Tanaka, Y. Kamiya, N. Irie, A. Fujimaki, Y. Yamanashi, A. Akimoto, H. Park, N. Yoshikawa, H. Terai, S. Yorozu. “ A new design approach for high-throughput arithmetic circuits for single-flux-quantum” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EB06.

(11)　H. Terai, Z. Wang, M .Tanaka, A Fujimaki, Y. Yamanashi, N. Yoshikawa, Y . Hashimoto, “Diagnostic Test of Large-Scale SFQ Shift Register” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 2EI05.

(12)　Q. Liu, K. Fujiwara, X. Meng, T. Van Duzer, N. Yoshikawa, Y. Thakahashi, T. Hikida, N. Kawai, “Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EB08.

(13)　Y. Yamanashi, T. Nishigai, N. Yoshikawa, “Study of LR-Loading Technique for Low-Power Single Flux Quantum Circuits” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 1EX07

(14)　Y. Yamanashi, A. Akimoto, H. Park, N. Yoshikawa, M. Tanaka, Y. Kamiya, N. Irie, A. Fujimaki, H Terai, S. Yorozu, “Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1b” Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 3EY01

(15)　H. Park, Y. Yamanashi, N .Yoshikawa, A. Fujimaki, M. Tanaka, H. Terai, S. Yorozu, “Design of Bit-Slice Adders Using RSFQ Logic Circuits” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 3EY03.

(16)　G. Matsuda, Y. Yamanashi, N. Yoshikawa, “Design of an SFQ Microwave Chopper for Controlling Quantum Bits” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 1EX05.

(17)　T. Hikida, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, NICT; S. Yorozu, “Bit-Error-Rate Measurements of RSFQ Shift Register Memories” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 4EB05.

(18)　Y. Takahashi, M. Tokuda, N. Kawai, N. Yoshikawa, K. Fujiwara, Q. Liu, T. Van Duzer, “Access-Time Measurements of a Josephson-CMOS Hybrid Memory using an RSFQ Time-to-Digital Converter” , Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 2EI03.

(19)　Y. Nobumori, T. Nishigai, K. Nakamiya, N. Yoshikawa, A. Fujimaki, H. Terai, NICT; S. Yorozu, “Design and Implementation of a Fully Asynchronous RSFQ Microprocessor: SCRAM2” Abstract of 2006 Applied Superconductivity Conference (ASC2006), Seattle, Washington, September 2006, 3EY02.

(20)　A. Fujimaki, M. Tanaka, N. Irie, S. Iwasaki, T. Yamada, N. Takagi, H. Park, Y. Yamanashi, N. Yoshikawa, H. Terai, S. Yorozu, Y. Takai, “Development of High-speed Single-flux-quantum Microprocessors,” Abstracts on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 160

(21)　S. Iwasaki, M. Tanaka, N. Irie, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, “Quantative Evaluation of Delay Time in the Single-flux-Quantum Circuits,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 161

(22)　Y. Yamanashi, N. Yoshikawa, “Study on a DC-powered On-chip Voltage Generator Using SFQ Circuits,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 329.

(23)　T. Hikida, T. Nishigai, N. Yoshikawa, “Consideration of Low-power SFQ Circuits Using Josephson-junction-load Biasing,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 331.

(24)　K. Churei, H. Kojima, N. Yoshikawa, Y. Hashimoto, Y. Kameda, S. Yorozu, “Bit-error-rate Simulations of Josephson Latching Drivers Using the 10kA/cm2Nb Process,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 332.

(25)　K. Nakamiya, T. Nishigai, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, “Improvement of Time Resolution of the Double-Oscillator Time-to-digital Converter Using SFQ Circuits.” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 333.

(26)　N. Kawai, N. Yoshikawa, “Reduction of a Bit-error-rate of Josephson Latching Drivers Using Series Inductors,” on 19th International Symposium on Superconductivity (ISS2006), Nagoya, October 2006, pp. 334.

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​

2007

 

(1)　H. Terai, M. Tanaka, Y. Yamanashi, Y. Hashimoto, A. Fujimaki, N. Yoshikawa, Z. Wang, “Diagnostic Test of Large-Scale SFQ Shift Register ”, IEEE Transactions on Applied Superconductivity, vol. 17, issue 2, part 1, pp. 422-425, June 2007.

(2)　Y. Yamanashi, M. Tanaka, A. Akimoto, H. Park, Y. Kamiya, N. Irie, N. Yoshikawa, A. Fujimaki, H. Terai, Y. Hashimoto, “Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β” , IEEE Transactions on Applied Superconductivity, vol. 17, issue 2, part 1, pp. 474-477, June 2007.

(3)　Y. Nobumori, T. Nishigai, K. Nakamiya, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, “Design and Implementation of a Fully Asynchronous SFQ Microprocessor: SCRAM2”, IEEE Transactions on Applied Superconductivity, vol. 17, issue 2, part 1, pp. 478-481, June 2007.

(4)　T. Hikida, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, “Bit-Error-Rate Measurements of RSFQ Shift Register Memories”, IEEE Transactions on Applied Superconductivity, vol. 17, issue 2, part 1, pp. 512-515, June 2007.

(5)　M. Tanaka, Y. Yamanashi, Y. Kamiya, A. Akimoto, N. Irie, H. Park, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, “A New Design Approach for High-Throughput Arithmetic Circuits for Single-Flux-Quantum Microprocessors” , IEEE Transactions on Applied Superconductivity, vol. 17, issue 2, part 1, pp. 516-519, June 2007.

(6)　K. Nakamiya, T. Nishigai, N. Yoshikawa, A. Fujimaki, H. Terai, S. Yorozu, “Improvement of time resolution of the double-oscillator time-to-digital converter using SFQ circuits” , Physica C: Superconductivity and its applications, vol. 463-465, pp. 1088-1091, October 2007.

(7)　M. Tanaka, Y. Yamanashi, N. Irie, H. Park, S. Iwasaki, K. Takagi, K. Taketomi, A. Fujimaki, N. Yoshikawa, H. Terai, S. Yorozu, “Design and implementation of a pipelined 8 bit-serial single-flux-quantum microprocessor with cache memories” , Superconductor Science and Technology, vol. 20, no. 11, pp. S305-S309, Nobember 2007.

(8)　S. Iwasaki, M. Tanaka, Y. Yamanashi, H. Park, H. Akaike, A. Fujimaki, N. Yoshikawa, N. Takagi, K. Murakami, H. Honda, K. Inoue, “Design of a reconfigurable data-path prototype in the single-flux-quantum circuit” , Superconductor Science and Technology, vol. 20, no. 11, pp. S328-S331, Nobember 2007.

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​

2008

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(1)　H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, A. Fujimaki, N. Takagi, “Novel serial-parallel converter using SFQ logic circuits,” Physica C, Vol. 468, pp. 1977-1982, May 2008.

(2)　K. Nakamiya, N. Yoshikawa, A. Fujimaki, H. Terai, Y. Hashimoto, “Direct measurements of propagation delay of single-flux-quantum circuits by time-to-digital converters” , IEICE Electronics Express, Vol. 5 (2008) , No. 9, pp.332-337.

(3)　A. Fujimaki, M. Tanaka, T. Yamada, Y. Yamanashi, H. Park, N. Yoshikawa, “Bit-Serial Single Flux Quantum Microprocessor CORE,” IEICE TRANSACTIONS on Electronics, vol. E91-C, no.3, pp. 342-349, March 2008.

(4)　N. Takagi, K. Murakami, A. Fujimaki, N. Yoshikawa, K. Inoue, H. Honda, “Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits,” vol. E91-C, no.3, pp. 350-355, March 2008.

(5)　山梨裕希, 吉川信行, 田中雅光, 藤巻朗, “超伝導回路による超高速・低消費電力マイクロプロセッサの開発” 電気学会A部門誌, 2008年6月号 (解説論文)

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2009

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(1)　H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, M. Tanaka, K. Obata, Y. Itou, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa, “Design and Implementation of SFQ Half-Precision Floating-Point Adders”, IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 634-639.

(2)　H. Hara, H. Park, Y. Yamanashi, K. Taketomi, N. Yoshikawa, K. Obata, M. Tanaka, N. Takagi, K. Takagi, A. Fujimaki, S. Nagasawa,“Design and Implementation of SFQ Half-Precision Floating-Point Multipliers” , IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 657-660.

(3)　Y. Yamanashi, and N. Yoshikawa, “Superconductive Random Number Generator Using Thermal Noises in SFQ Circuits” , IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 630-633.

(4)　M. Igarashi, K. Churei, N. Yoshikawa ,K. Fujiwara, Y. Hashimoto, “SFQ pulse transfer circuits using inductive coupling for current recycling ”, IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 649-652.

(5)　I. Kataeva, H. Akaike, A. Fujimaki, N. Takagi, N. Yoshikawa, K. Inoue, H. Honda, K. Murakami, “An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor” , IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 665-669.

(6)　T. Satoh, K. Hinode, S. Nagasawa, Y. Kitagawa, M. Hidaka, N. Yoshikawa, H. Akaike, A. Fujimaki, K. Takagi, N. Takagi, “Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer”, IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 167-170.

(7)　M. Tanaka, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, N. Yoshikawa, “A high-throughput single-flux-quantum floating-point serial divider using the signed-digit representation” , IEEE Trans. Appl. Superconductivity, vol. 19, 2009, pp. 653-656.

(8)　N. Takeuchi, Y. Yamanashi, Y. Saito, N. Yoshikawa, “3D simulation of superconducting microwave devices with an electromagneticfield simulator” Physica C, vol. 469, 2009, pp.1662-1665.

(9)　H. Park, Y. Yamanashi, N. Yoshikawa, M. Tanaka and A. Fujimaki, “Design of fast digit-serial adders using SFQ logic circuits,” IEICE Electron. Express, vol. 6, 2009, pp.1408-1413.

(10)　吉川信行，“単一磁束量子回路を制御回路とする量子計算システム,” 応用物理, 第78巻, 第１号, 2009, pp. 22-26.

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​

2010

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(1)　K. Fujiwara, Q. Liu, T. Van Duzer, X. Meng, N. Yoshikawa, “New delay-time measurements on a 64 kb Josephson-CMOS hybrid memory with 600 ps access time,” IEEE Trans. Appl. Superconductivity, vol. 20, 2010, pp. 14-20.

(2)　Y. Yamanashi, T. Kainuma, N. Yoshikawa, I. Kataeva, H. Akaike, A. Fujimaki, M. Tanaka, N. Takagi, S. Nagasawa, M. Hidaka, “100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process,” IEICE Trans. Electron., vol. E93-C, April 2010, pp. 440-444.

(3)　T. Sugiura, Y. Yamanashi, N. Yoshikawa, “Statistical Evaluation of a Superconductive Physical Random Number Generator,” IEICE Trans. Electron., vol. E93-C, April 2010, pp. 453-457.

(4)　N. Takeuchi, Y. Yamanashi and N. Yoshikawa, “Design and Implementation of RSFQ Microwave Choppers for the Superconducting Quantum-Computing System,” IEICE Trans. Electron., vol. E93-C, April 2010, pp. 458-462.

(5)　N. Takeuchi, D. Ozawa, Y. Yamanashi, N. Yoshikawa, “On-chip RSFQ microwave pulse generator using a multi-flux-quantum driver for controlling superconducting qubits,” Physica C, vol. 470, May 2010, pp. 1550-1554.

(6)　Y. Okamoto, H. Jin, K. Yaguchi, Y. Yamanashi, and N. Yoshikawa, “Access Time Measurement of 64-kb Josephson-CMOS Hybrid Memories using SFQ Time-to-Digital Converter,” IEICE Electron. Express, vol. 7, 2010, pp.320-325.

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​

2011

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(1)　Y. Yamanashi, I. Okawa, N. Yoshikawa, “Design Approach of Dynamically Reconfigurable Single Flux Quantum Logic Gates,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 831-834.

(2)　D. Ozawa, Y. Yamanashi, N. Yoshikawa, “Design and Evaluation of Multi-Flux-Quantum Drivers Using Under-Damped Josephson Junctions,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 835-838.

(3)　T. Sugiura, Y. Yamanashi, N. Yoshikawa, “Demonstration of 30 Gbit/s Generation of Superconductive True Random Number Generator,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 843-846.

(4)　T. Kainuma, Y. Shimamura, F. Miyaoka, Y. Yamanashi, N. Yoshikawa, A.Fujimaki, K. Takagi, N.Takagi, S.Nagasawa, “Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm2 Nb Process,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 827-830.

(5)　I. Kataeva, H. Akaike, A. Fujimaki, N. Yoshikawa, S. Nagasawa, N. Takagi, “Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 809-813.

(6)　F. Miyaoka, T. Kainuma, Y. Shimamura, Y. Yamanashi, N. Yoshikawa, “High-Speed Test of a Radix-2 Butterfly Processing Element for Fast Fourier Transforms Using SFQ Circuits,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 823-826.

(7)　Y. Arita, N. Yoshikawa, T. Baba, “Integration of Optical Waveguides With Single Flux Quantum Circuits,” IEEE Trans. Appl. Superconductivity, vol. 21, 2011, pp. 839-842.

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​

2012

​

(1)　S. Miura, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Implementation of SFQ Microwave Choppers for Controlling Quantum Bits,” Physics Procedia, vol. 36, 2012, pp. 250-255.

(2)　Hyunjoo Jin, Keita Kuwabara, Yuki Yamanashi, Nobuyuki Yoshikawa, “Investigation of Robust CMOS Amplifiers for Josephson-CMOS Hybrid Memories,” Physics Procedia, vol. 36, 2012, pp. 229-234.

(3)　Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Naofumi Takagi, “Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme,” Physics Procedia, vol. 36, 2012, pp. 349-353.

(4)　Koji Suzuki, Masahiro Ukibe, Shigetomo Shiki, Shigehito Miki, Zhen Wang, Yoshihiro Takahashi, Nobuyuki Yoshikawa, Masataka Ohkubo, “Pulse-Height Distribution Analysis for Superconducting Nanostripline Ion Detector with a Fast Pulse-Integration Analog-Todigital Converter,” Physics Procedia, vol. 36, 2012, pp. 172-176.

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​

2013

 

(1)　N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, "Simulation of sub-kBT bit-energy operation of adiabatic quantum-flux-parametron logic with low bit-error-rate," Appl. Phys. Lett., vol. 103, no. 6, p. 062602, 2013 (4pp).

(2)　T. Mukaiyama, N. Takeuchi, K. Ehara, K. Inoue, Y. Yamanashi, and N. Yoshikawa, "Operation of an Adiabatic Quantum-Flux-Parametron Gate Using an On-Chip AC Power Source," IEEE Trans. Appl. Supercond., vol. 23, no. 4, pp. 1301605, Aug. 2013 (5pp).

(3)　N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "Measurement of 10 zJ energy dissipation of adiabatic quantum-flux-parametron logic using a superconducting resonator," Appl. Phys. Lett., 102, 052602 (2013).

(4)　N. Takeuchi, D. Ozawa, Y. Yamanashi and N. Yoshikawa, "Adiabatic quantum flux parametron as an ultra-low-power logic device," Supercond. Sci. Tech., vol. 26, 2013, 035010 (5pp).

(5)　T. Mukaiyama, N. Takeuchi, Y. Yamanashi and N. Yoshikawa, "Design and Demonstration of an On-chip AC Power Source for Adiabatic Quantum-Flux-Parametron Logic," Supercond. Sci. Tech., vol. 26, 2013, 035018 (6pp).

(6)　N. Takeuchi, K. Ehara, K. Inoue, Y. Yamanashi and N. Yoshikawa, "Margin and Energy Dissipation of Adiabatic Quantum-Flux-Parametron Logic at Finite Temperature," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1700304 (4pp).

(7)　K. Inoue, N. Takeuchi, K. Ehara, Y. Yamanashi, and N. Yoshikawa, "Simulation and Experimental Demonstration of Logic Circuits Using an Ultra-low-power Adiabatic Quantum-flux-parametron," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1301105 (5pp).

(8)　K. Kuwabara, H. Jin, Y. Yamanashi and N. Yoshikawa, "Design and implementation of 64-kb CMOS static RAMs for Josephson-CMOS hybrid memories," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1700704 (4pp).

(9)　K. Ehara, A. Takahashi, Y. Yamanashi, N. Yoshikawa, "Development of pulse transfer circuits for serially biased SFQ circuits using the Nb 9-layer 1-μm process," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1300504 (4pp).

(10)　K. Aoki, Y. Yamanashi, and N. Yoshikawa, "Multiplexing Techniques of Single Flux Quantum Circuit Based Readout Circuit for a Multi-Channel Sensing System," IEEE Trans. Appl. Supercond., vol. 23, 2013, 2500204 (4pp).

(11)　M. Otsubo, Y. Yamanashi, and N. Yoshikawa, "Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1300904 (4pp).

(12)　Y. Tsuga, Y. Yamanashi, and N. Yoshikawa, "Asynchronous Digital SQUID Magnetometer With an On-Chip Magnetic Feedback for Improvement of Magnetic Resolution," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1601405 (4pp).

(13)　Y. Yamanashi, K. Umeda, and N. Yoshikawa, "Pseudo Sigmoid Function Generator for a Superconductive Neural Network," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1701004 (4pp).

(14)　M. Dorojevets, C. L. Ayala, N. Yoshikawa and A. Fujimaki, "16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1700605 (5pp).

(15)　M. Dorojevets, A. K. Kasperek, Member, N. Yoshikawa, and A. Fujimaki, "20-GHz 8 x 8-bit Parallel Carry-Save Pipelined RSFQ Multiplier," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1300104 (4pp).

(16)　M. Dorojevets, C. L. Ayala, N. Yoshikawa and A. Fujimaki, "8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of Operations," IEEE Trans. Appl. Supercond., vol. 23, 2013, 1700104 (4pp).

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​

2014

​

(1)　K. Sano, Y. Yamanashi, N. Yoshikawa, “Design and Demonstration of a Single-Flux-Quantum Multi-Stop Time-to-Digital Converter for Time-of-Flight Mass Spectrometry,” IEICE Trans. Electron., vol. E97-C, 2014, pp. 182-187.

(2)　Y. Yamanashi, N. Yoshikawa, “Design and Evaluation of Magnetic Field Tolerant Single Flux Quantum Circuits for Superconductive Sensing Systems,” IEICE Trans. Electron., vol. E97-C, 2014, pp. 178-181.

(3)　H. Kataoka, H. Honda, F. Mehdipour, N. Yoshikawa, A. Fujimaki, H. Akaike, N. Takagi, K. Murakami, “A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits,” IEICE Trans. Electron., vol. E97-C, 2014, pp. 141-148.

(4)　S. Nagasawa, K. Hinode, T. Satoh, M. Hidaka, H. Akaike, A. Fujimaki, N. Yoshikawa, K. Takagi, N. Takagi, “Nb 9-layer fabrication process for superconducting large-scale SFQ circuits and its process evaluation,” IEICE Trans. Electron., vol. E97-C, 2014, pp. 132-140. DOI: 10.1587/transele.E97.C.132

(5)　X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, M. Hidaka, “Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process,” IEICE Trans. Electron., vol. E97-C, 2014, pp. 188-193.

(6)　A. Fujimaki, M. Tanaka, R. Kasagi, K. Takagi, M. Okada, Y. Hayakawa, K. Takata, H. Akaike, N. Yoshikawa, S. Nagasawa, K. Takagi, N. Takagi, “Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors,” IEICE Trans. Electron., vol. E97-C, 2014, pp. 157-165. DOI: 10.1587/transele.E97.C.157

(7)　K. Sano, Y. Muramatsu, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Reduction of the Jitter of Single-Flux-Quantum Time-to-Digital Converters for Time-of-Flight Mass Spectrometry,” Physica C, vol. 504, 2014, pp. 97-101.

(8)　N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Novel latch for adiabatic quantum-flux-parametron logic,” Journal of Appl. Physics, vol. 115, 2014, 103910 (4pp).

(9)　D. Si, K. Inoue, Y. Yamanashi, N. Yoshikawa, “Yield analysis of large-scale adiabatic-quantum-flux-parametron logic: The effect of the distribution of the critical current,” Physica C, vol. 504, 2014, pp. 102-105.

(10)　N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “(Invited) High-speed Experimental Demonstration of Adiabatic Quantum-Flux-Latches,” IEEE Trans. Appl. Supercond., vol. 24, 2014,1300204 (4pp).

(11)　N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Reversible logic gate using adiabatic superconducting devices,” Scientific Reports, vol. 4, 2014, 6354.

(12)　N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Reversible Computing Using Adiabatic Superconductor Logic,” Lecture Notes in Computer Science, Vol. 8507, 2014, pp 15-25.

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​

2015

 

(1)　N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Energy efficiency of adiabatic superconductor logic,” Supercond. Sci. Technol., vol. 28, 2015, 015003 (5pp).DOI: 10.1088/0953-2048/28/1/015003

(2)　K. Inoue, N. Takeuchi, T. Narama, Y. Yamanashi, N. Yoshikawa, “Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields,” Supercond. Sci. Technol., vol. 28, 2015, 045020 (7pp). DOI: 10.1088/0953-2048/28/4/045020

(3)　Y. Sakashita, Y. Yamanashi, N. Yoshikawa, “50 GHz Demonstration of an Integer-Type Butterfly Processing Circuit for an FFT Processor Using the 10 kA/cm2 Nb Process,” IEICE Trans. Electron., vol. E98-C, March, 2015, pp. 232-237. DOI: 10.1587/transele.E98.C.232

(4)　Q. Xu, X. Peng, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Demonstration of Bit-Serial SFQ-Based Computing for Integer Iteration Algorithms,” IEEE Trans. on Appl. Supercond., 25, 2015, 1300704. DOI: 10.1109/TASC.2014.2374454

(5)　Y. Sakashita, Y. Yamanashi, N. Yoshikawa, “High-Speed Operation of an SFQ Butterfly Processing Circuit for FFT Processors Using the 10 kA/cm2 Nb Process,” IEEE Trans. on Appl. Supercond., 25, 2015, 1301205. DOI: 10.1109/TASC.2014.2384833

(6)　X. Peng, Q. Xu, T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi and M. Hidaka, “High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits,” IEEE Trans. on Appl. Supercond., 25, 2015, 1301106. DOI: 10.1109/TASC.2014.2382973

(7)　N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Adiabatic quantum-flux-parametron cell library adopting minimalist design,” Journal of Applied Physics, 117, 2015, 173912; DOI: 10.1063/1.4919838

(8)　K. Sano, Y. Takahashi, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, “Demonstration of single-flux-quantum readout circuits for time-of-flight mass spectrometry systems using superconducting strip ion detectors,” Supercond. Sci. Technol., vol.28, 2015, 074003 (5pp) DOI :10.1088/0953-2048/28/7/074003

(9)　C. J. Fourie, X. Peng, R. Numaguchi, N. Yoshikawa, “Inductance and Coupling of Stacked Vias in a Multilayer Superconductive IC Process,” IEEE Trans. Appl. Supercond., vol. 25, 2015, 1101104,. DOI : 10.1109/TASC.2014.2378013

(10)　C. J. Fourie, A. Takahashi, N. Yoshikawa, “Fast and accurate inductance and coupling calculation for a multi-layer Nb process,” Supercond. Sci. Technol., vol. 28, 2015, 035013,. DOI : 10.1088/0953-2048/28/3/035013

(11)　N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Thermodynamic Study of Energy Dissipation in Adiabatic Superconductor Logic,” Phys. Rev. Applied 4, 2015, 034007; DOI: 10.1103/PhysRevApplied.4.034007

(12)　S. Nishimoto, Y. Yamanashi, N. Yoshikawa, “Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates,” IEEE Trans. Appl. Supercond., vol. 25, 2015, 1301405,. DOI : 10.1109/TASC.2014.2387251

(13)　K. Sato, Y. Yamanashi, N. Yoshikawa, “High-Speed Operation of a Single Flux Quantum Multiple Input Merger Using a Magnetically Coupled SQUID Stack,” IEEE Trans. Appl. Supercond., vol. 25, 2015, 1301605,. DOI : 10.1109/TASC.2015.2398675

(14)　N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Experimental Demonstration of Quantum-Flux-Latch-Based Circuits,” IEEE Trans. Appl. Supercond., vol. 25, 2015, 1300803,. DOI : 10.1109/TASC.2014.2374472

(15)　N. Tsuji, N. Takeuchi, T. Narama, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Magnetically coupled quantum-flux-latch with wide operation margins,” Supercond. Sci. Technol., 28, 2015, 115013,. DOI : 10.1088/0953-2048/28/11/115013

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2016

 

(1)　C. Fourie, N. Takeuchi, N. Yoshikawa, "(Invited) Inductance and Current Distribution Extraction in Nb Multilayer Circuits with Superconductive and Resistive Components", IEICE Transactions on Electronics vol. E99-C, No. 6 June 2016, pp. 683-691,. DOI : 10.1587/transele.E99.C.683

(2)　N. Tsuji, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, "Majority Gate-Based Feedback Latches for Adiabatic Quantum Flux Parametron Logic", IEICE Transactions on Electronics vol. E99-C, No. 6 June 2016, pp. 710-716,. DOI : 10.1587/transele.E99.C.710

(3)　Y. Yamanashi, S. Nishimoto, and N. Yoshikawa, “30 GHz Operation of Single-Flux-Quantum Arithmetic Logic Unit Implemented by Using Dynamically Reconfigurable Gates”, IEICE Transactions on Electronics vol. E99-C, No. 6 June 2016, pp. 692-696,. DOI : 10.1587/transele.E99.C.692

(4)　F. China, T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, "Design and Demonstration of Interface Circuits between Rapid Single-Flux-Quantum and Adiabatic Quantum-Flux-Parametron Circuits", IEEE Trans. Appl. Supercond., vol. 26, No. 5, Aug. 2016, 1301305-1-5, DOI : 10.1109/TASC.2016.2577603

(5)　R. Kihara, Y. Yamanashi, N. Yoshikawa, "Power Reduction of Josephson Random Access Memory Using Stochastic Resonance", IEEE Trans. Appl. Appl. Supercond., Vol. 26, No. 8, Dec. 2016, 1301704-1-4, DOI: 10.1109/TASC.2016.2607156

(6)　R. Tsutsumi, K. Sato, Y. Yamanashi, N. Yoshikawa, "Improvement of Operation Speed of LR-Biased Low-Power Single-Flux Quantum Circuits by Introduction of Dynamic Resetting of Bias Currents", IEEE Trans. Appl. Appl. Supercond., Vol. 26, No. 8, Dec. 2016, 1301405-1-5, DOI: 10.1109/TASC.2016.2598766

(7)　Q. Xu, C. L. Ayala, Y. Yamanashi, N. Takeuchi, N. Yoshikawa, "HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic", IEEE Trans. Appl. Appl. Supercond., Vol. 26, No. 8, Dec. 2016, 1301805-1-5, DOI: 10.1109/TASC.2016.2615123

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2017

 

(1)　 N. Takeuchi, S. Nagasawa, F. China, T. Ando, M. Hidaka, Y. Yamanashi, N. Yoshikawa, “Adiabatic quantum-flux-parametron cell library designed using a 10 kA cm−2 niobium fabrication process,” Superconductor Science and Technology, vol. 30, No. 3, Jan. 2017, pp 035002-1-6. DOI:10.1088/1361-6668/aa52f3

(2)　 C. L. Ayala, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa, “Majority-logic-optimized parallel prefix carry look-ahead adder families using adiabatic quantum-flux-parametron logic,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1300407-1-7. DOI: 10.1109/TASC.2016.2642041

(3)　 F. China, N. Tsuji, T. Narama, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Demonstration of Signal Transmission Between Adiabatic Quantum-Flux-Parametrons and Rapid Single-Flux-Quantum Circuits Using Superconductive Microstrip Lines,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1300205-1-5. DOI: 10.1109/TASC.2016.2642046

(4)　 G. Konno, Y. Yamanashi, N. Yoshikawa, “(Invited) Fully Functional Operation of Low-Power 64-kb Josephson-CMOS Hybrid Memories,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1300607-1-7. DOI: 10.1109/TASC.2016.2646911

(5)　 T. Ono, H. Suzuki, Y. Yamanashi, N. Yoshikawa, “Design and Implementation of an SFQ-Based Single-Chip FFT Processor,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1301505-1-5. DOI: 10.1109/TASC.2017.2667398

(6)　 K. Sano, T. Shimoda, Y. Abe, Y. Yamanashi, N. Yoshikawa, “Reduction of the Supply Current of Single-Flux-Quantum Time-to-Digital Converters by Current Recycling Techniques,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1300305-1-5. DOI: 10.1109/TASC.2016.2646916

(7)　 M. Tanaka, M. Suzuki, G. Konno, Y. Ito, A.Fujimaki, N. Yoshikawa, “Josephson-CMOS Hybrid Memory With Nanocryotrons,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1800904-1-4. DOI: 10.1109/TASC.2016.2646929

(8)　 N. Tsuji, C. L. Ayala, N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa, “Design and Implementation of a 16-Word by 1-Bit Register File Using Adiabatic Quantum Flux Parametron Logic,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1300904-1-4. DOI: 10.1109/TASC.2017.2656128

(9)　 Qiuyun Xu, C. L. Ayala, N. Takeuchi, Y. Murai, Y. Yamanashi, N. Yoshikawa, “Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation With HDL Back-End Verification,” IEEE Trans. Appl. Supercond. vol. 27, 2017, 1301905-1-5. DOI: 10.1109/TASC.2017.2662017

(10)　 N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Reversibility and energy dissipation in adiabatic superconductor logic,” Scientific Reports, 7, 2017, 75-1-12. DOI: 10.1038/s41598-017-00089-9

(11)　 K. Fang, N. Takeuchi, T. Ando, Y. Yamanashi, N. Yoshikawa, “Multi-excitation adiabatic quantum-flux-parametron,” Journal of Applied Physics, 121, 2017, 143901. DOI:10.1063/1.4979856

(12)　 T. Ando, S. Nagasawa, N. Takeuchi, N. Tsuji, F. China, M. Hidaka, Y. Yamanashi, N. Yoshikawa, “Three-dimensional adiabatic quantum-flux-parametron fabricated using a double-active-layered niobium process,” Supercond. Sci. Technol. vol. 30, 2017, 075003 (7pp). DOI: 10.1088/1361-6668/aa6ef4

(13)　 Y. Yamanashi, T. Matsushima, N. Takeuchi, N. Yoshikawa and T. Ortlepp, “Evaluation of current sensitivity of quantum flux parametron,” Supercond. Sci. Technol. vol. 30, 2017, 084004 (5pp). DOI: 10.1088/1361-6668/aa73be

(14)　 Y. Murai, Christopher L. Ayala, N. Takeuchi, Y. Yamanashi, and N. Yoshikawa, “Development and Demonstration of Routing and Placement EDA Tools for Large-Scale Adiabatic Quantum-Flux-Parametron Circuits,” IEEE Transactions on Applied Superconductivity, vol. 27, 2017, 1302209. DOI: 10.1109/TASC.2017.271965

(15)　 H. Suzuki, T. Ono, N. Yoshikawa, “Experimental and simulation results of a symmetrical pad to reduce a stray ground current in superconducting integrated circuits,” Journal of Physics. Conference Series. vol. 871, 2017, 012067. DOI: 10.1364/OE.25.032650

(16)　 N. Takeuchi, T. Yamashita, S. Miyajima, S. Miki, N. Yoshikawa, G. Terai “Adiabatic quantum-flux-parametron interface for the readout of superconducting nanowire single-photon detectors,” Optics Express, Vol. 25, Issue 26, pp. 32650-32658, 2017, DOI: 10.1364/OE.25.032650

(17)　 N. Takeuchi, H. Suzuki, N. Yoshikawa, “Measurement of low bit-error-rates of adiabatic quantum-flux-parametron logic using a superconductor voltage driver,” Appl. Phys. Lett., 110, 202601 (2017) . DOI: 10.1063/1.4983351

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2018

 

(1)　"N. Takeuchi, N. Yoshikawa, “Minimum energy dissipation required for a logically irreversible operation,” Phys. Rev. E 97, 012124, 2018 (5pp). DOI: 10.1103/PhysRevE.97.012124"

(2)　"N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “(Invited Paper) Recent Progress on Reversible Quantum-Flux-Parametron for Superconductor Reversible Computing,” IEICE Transaction on Electronics, E101-C (2018) NO.5, Pages 352-358, 2018. DOI: 10.1587/transele.E101.C.352"

(3)　"K. Sano, M. Suzuki, K. Maruyama, S. Taniguchi, M. Tanaka, A. Fujimaki, M. Inoue, N. Yoshikawa, “(Invited Paper) Thermally Assisted Superconductor Transistors for Josephson-CMOS Hybrid Memories,” IEICE Transaction on Electronics, vol. E101-C (2018) NO.5, pp. 370-377, May 2018. DOI: 10.1587/transele.E101.C.370"

(4)　"Y. Yamanashi, S. Nakaishi1, A. Sugiyama, N. Takeuchi, N. Yoshikawa, “Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions,” Supercond. Sci. Technol. 31 (2018) 105003 (7pp). DOI: 10.1088/1361-6668/aad78d"

(5)　"H. Takayama, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “A random-access-memory cell based on quantum flux parametron with three control lines,” Journal of Physics. Conf. Series. 1054 (2018) 012063. DOI: 10.1088/1742-6596/1054/1/012063"

(6)　"C. J. Fourie, K. Jackman, M. M. Botha, S. Razmkhah, P. Febvre, C. L. Ayala, Q. Xu, N. Yoshikawa, E. Patrick, M. Law, Y. Wang M. Annavaram P. Beerel S. Gupta S. Nazarian M. Pedram “ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress,” IEEE Trans. Appl. Supercond. vol. 29, 2018, 1300407-1-7. DOI: 10.1109/TASC.2019.2892115"

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2019

 

(1)　"T. Yamae, N. Takeuchi, N. Yoshikawa, “A reversible full adder using adiabatic superconductor logic,” Supercond. Sci. Technol. 32 (2019) 035005 (8pp). DOI: 10.1088/1361-6668/aaf8c9"

(2)　"K. Arai, N. Takeuchi, T. Yamashita, N. Yoshikawa, “Adiabatic quantum-flux-parametron with π Josephson junctions,” Journal of Applied Physics 125, 093901 (2019). DOI:10.1063/1.5080467"

(3)　"N. Yoshikawa, “(Invited Paper) Superconducting Digital Electronics for Controlling Quantum Computing Systems, ” IEICE Trans Electron, vol.E102–C, NO.3 March 2019."

(4)　"Y. He, G. Macchiarella, Z. Ma, L. Sun, N. Yoshikawa, “Advanced Direct Synthesis Approach for High Selectivity In-Line Topology Filters Comprising N - 1 Adjacent Frequency-Variant Couplings,” IEEE Access, vol. 7, 2019. pp. 41659-41668. DOI:10.1109/ACCESS.2019.2907531"

(5)　"Y. Yamanashi, S. Nakaishi, N. Yoshikawa, “(Invited Paper) Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions,” IEEE Trans. Appl. Supercond. vol. 29, NO.5, AUGUST 2019, 1301805-1-5. DOI:10.1109/TASC.2019. 2904700"

(6)　"N. Takeuchi, T. Yamashita, S. Miyajima, S. Miki, N. Yoshikawa, H. Terai, “Demonstration of a Superconducting Nanowire Single-Photon Detector using Adiabatic Quantum-Flux-Parametron Logic in a 0.1-W Gifford-McMahon Cryocooler,” IEEE Trans. Appl. Supercond. vol. 29, NO.5, AUGUST 2019, 2201004-1-4. DOI:10.1109/TASC.2019.2902771"

(7)　"T. Tanaka, C. L. Ayala, Q. Xu, R. Saito, N. Yoshikawa, “Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms,” IEEE Transactions on Applied Superconductivity, vol. 29, NO.5, AUGUST 2019, 1301706. DOI: 10.1109/TASC.2019.2900220"

(8)　"Y. Tomitsuka, Y. Yamanashi, N. Zen, M. Ohkubo, N. Yoshikawa, “Demonstration of Picosecond Time Resolution in Double-Oscillator Time-to-Digital Converter UsingSingle-Flux-Quantum Circuits,” IEEE Transactions on Applied Superconductivity, vol. 29, NO.5, AUGUST 2019, 1301505. DOI: 10.1109/TASC.2019.2902478"

(9)　"A. Sanada, Y. Yamanashi, N. Yoshikawa, “Study on Single Flux Quantum Floating-Point Divider Based on Goldschmidt’s Algorithm,” IEEE Trans. Appl. Supercond. vol. 29, vol. 29, NO.5, AUGUST 2019, 1301904-1-4. DOI:10.1109/TASC.2019. 2902800"

(10)　"O. Chen, R. Saito, T. Tanaka, C. L. Ayala, N. Takeuchi and N. Yoshikawa, ""Design of Adiabatic Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow,"" in IEEE Transactions on Applied Superconductivity, vol. 29, no. 5, pp. 1-5, Aug. 2019, Art no. 1302905. DOI: 10.1109/TASC.2019.2908277"

(11)　"N. Takeuchi, C. L. Ayala, O. Chen, N. Yoshikawa “A Feedback-Friendly Large-Scale Clocking Scheme for Adiabatic Quantum-Flux-Parametron Logic Datapaths,” IEEE Trans. Appl. Supercond. vol. 29, NO.5, August 2019, 1302505-1-5. DOI:10.1109/TASC.2019. 2904480"

(12)　"Y. Okuma, N. Takeuchi, Y. Yamanashi, N. Yoshikawa “Miniaturization of adiabatic quantum-flux-parametron circuits by adopting offset buffers,” Superconductor Science and Technology 32, 065007, 2019. DOI: 10.1088/1361-6668/ab1672"

(13)　"N. Takeuchi, M. Aono, N. Yoshikawa “Superconductor Amoeba-Inspired Problem Solvers for Combinatorial Optimization,” Phys. Rev. Applied 11, 044069 – Published 22 April 2019. DOI: 10.1103/PhysRevApplied.11.044069"

(14)　"O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi and N. Yoshikawa, "" Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems,"" Scientific Reports 9, Article number: 10514 (2019) , Published 19 July 2019. DOI: 10.1038/s41598-019-46595-w"

(15)　"Y. Okuma, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and Demonstration of an Adiabatic-Quantum-Flux-Parametron Field-Programmable Gate Array Using Josephson-CMOS Hybrid Memories,” IEEE Trans. Appl. Supercond. vol. 29, NO.8, December 2019, 1103606-1-6. DOI: 10.1109/TASC.2019.2938577"

(16)　"T. Yamae, N. Takeuchi, N. Yoshikawa, “Systematic method to evaluate energy dissipation in adiabatic quantum-flux-parametron logic,” J. Appl. Phys. 126, 173903 (2019). DOI: 10.1063/1.5119306 "

(17)　"N. Takeuchi, T. Yamae, C. L. Ayala, H. Suzuki, N. Yoshikawa, “An adiabatic superconductor 8-bit adder with 24kBT energy dissipation per junction,” Appl. Phys. Lett., 114, 042602 (2019). DOI: 10.1063/1.5080753 "

(18)　"N. Takeuchi, M. Nozoe, Y. He, N. Yoshikawa, “Low-latency adiabatic superconductor logic using delay-line clocking,” Appl. Phys. Lett., 115, 072601 (2019). DOI: 10.1063/1.5111599"

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